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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc83082 /*192785*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
94785 /*215162*/ /*SwitchOpcode*/ 24|128,3/*408*/, TARGET_VAL(ISD::SHL),// ->215574
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7737 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc 82 /* 65*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
93 /* 84*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
111 /* 116*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
122 /* 136*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
139 /* 166*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
150 /* 186*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
167 /* 216*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
178 /* 236*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
195 /* 266*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
206 /* 286*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
223 /* 316*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
234 /* 336*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
251 /* 366*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
262 /* 386*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
325 /* 518*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
336 /* 538*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
353 /* 568*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
364 /* 588*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
381 /* 618*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
392 /* 638*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
409 /* 668*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
420 /* 688*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
437 /* 718*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
448 /* 738*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
465 /* 768*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
476 /* 788*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
508 /* 865*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
519 /* 884*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
538 /* 917*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
549 /* 937*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
566 /* 967*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
577 /* 987*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
594 /* 1017*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
605 /* 1037*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
622 /* 1067*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
633 /* 1087*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
650 /* 1117*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
661 /* 1137*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
678 /* 1167*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
689 /* 1187*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
752 /* 1319*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
763 /* 1339*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
780 /* 1369*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
791 /* 1389*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
808 /* 1419*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
819 /* 1439*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
836 /* 1469*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
847 /* 1489*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
864 /* 1519*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
875 /* 1539*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
892 /* 1569*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
903 /* 1589*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
28032 /* 58785*/ OPC_SwitchOpcode /*2 cases */, 37, TARGET_VAL(ISD::SHL),// ->58826
28211 /* 59139*/ OPC_SwitchOpcode /*6 cases */, 27, TARGET_VAL(ISD::SHL),// ->59170
28289 /* 59298*/ OPC_SwitchOpcode /*6 cases */, 26, TARGET_VAL(ISD::SHL),// ->59328
47717 /*102782*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
47816 /*102984*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
52653 /*114217*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
52672 /*114267*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
52694 /*114330*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
52714 /*114381*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
52917 /*114866*/ /*SwitchOpcode*/ 90|128,1/*218*/, TARGET_VAL(ISD::SHL),// ->115088
52923 /*114879*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
54508 /*119479*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SHL),// ->119509
54540 /*119544*/ OPC_SwitchOpcode /*3 cases */, 26, TARGET_VAL(ISD::SHL),// ->119574
59991 /*131233*/ /*SwitchOpcode*/ 63, TARGET_VAL(ISD::SHL),// ->131299
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 60 /* 9*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
158 /* 368*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
324 /* 863*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
359 /* 1003*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
397 /* 1157*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
433 /* 1298*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
7926 /* 30251*/ /*SwitchOpcode*/ 82|128,1/*210*/, TARGET_VAL(ISD::SHL),// ->30465
gen/lib/Target/ARC/ARCGenDAGISel.inc 697 /* 1161*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SHL),// ->1212
gen/lib/Target/ARM/ARMGenDAGISel.inc 63 /* 15*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
110 /* 105*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
143 /* 175*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
215 /* 324*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
283 /* 463*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
336 /* 572*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
517 /* 986*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
582 /* 1120*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
643 /* 1247*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
3906 /* 7971*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
3924 /* 8009*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::SHL),// ->8057
3961 /* 8079*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
3980 /* 8118*/ /*SwitchOpcode*/ 46, TARGET_VAL(ISD::SHL),// ->8167
26444 /* 57101*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::SHL),// ->57137
35363 /* 77968*/ /*SwitchOpcode*/ 56|128,1/*184*/, TARGET_VAL(ISD::SHL),// ->78156
gen/lib/Target/ARM/ARMGenFastISel.inc 5177 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6191 case ISD::SHL: return fastEmit_ISD_SHL_ri(VT, RetVT, Op0, Op0IsKill, imm1);
6798 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_imm1_31(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/AVR/AVRGenDAGISel.inc 799 /* 1327*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::SHL),// ->1345
gen/lib/Target/BPF/BPFGenDAGISel.inc 1502 /* 2602*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::SHL),// ->2676
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc14814 /* 28157*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14838 /* 28198*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14904 /* 28332*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14925 /* 28368*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
15669 /* 29964*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
15716 /* 30050*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
15788 /* 30183*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
17202 /* 32941*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
17226 /* 32982*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
17257 /* 33037*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
17486 /* 33461*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
17510 /* 33502*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
17541 /* 33557*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
17770 /* 33981*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
17794 /* 34022*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
17825 /* 34077*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18054 /* 34501*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18078 /* 34542*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18109 /* 34597*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18338 /* 35021*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18362 /* 35062*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18393 /* 35117*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18622 /* 35541*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18646 /* 35582*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18677 /* 35637*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18906 /* 36061*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18930 /* 36102*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18961 /* 36157*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19198 /* 36611*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19226 /* 36667*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19252 /* 36721*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19280 /* 36776*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
20209 /* 38585*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
20267 /* 38690*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
20284 /* 38720*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
20326 /* 38796*/ OPC_SwitchOpcode /*2 cases */, 30, TARGET_VAL(ISD::SHL),// ->38830
20363 /* 38867*/ OPC_SwitchOpcode /*5 cases */, 49|128,4/*561*/, TARGET_VAL(ISD::SHL),// ->39433
20426 /* 38987*/ OPC_SwitchOpcode /*2 cases */, 107, TARGET_VAL(ISD::SHL),// ->39098
20495 /* 39114*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
20585 /* 39277*/ OPC_SwitchOpcode /*2 cases */, 73, TARGET_VAL(ISD::SHL),// ->39354
20634 /* 39370*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
20689 /* 39475*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
20708 /* 39518*/ OPC_SwitchOpcode /*2 cases */, 89|128,3/*473*/, TARGET_VAL(ISD::SHL),// ->39996
20748 /* 39589*/ OPC_SwitchOpcode /*2 cases */, 73, TARGET_VAL(ISD::SHL),// ->39666
20798 /* 39683*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
20845 /* 39773*/ OPC_SwitchOpcode /*2 cases */, 107, TARGET_VAL(ISD::SHL),// ->39884
20915 /* 39901*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
20976 /* 40014*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
21017 /* 40084*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
21064 /* 40174*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
21127 /* 40291*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
21167 /* 40360*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
21214 /* 40450*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
21393 /* 40806*/ /*SwitchOpcode*/ 50, TARGET_VAL(ISD::SHL),// ->40859
21518 /* 41031*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::SHL),// ->41086
21620 /* 41218*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::SHL),// ->41252
21676 /* 41327*/ /*SwitchOpcode*/ 0|128,9/*1152*/, TARGET_VAL(ISD::SHL),// ->42483
21709 /* 41391*/ OPC_SwitchOpcode /*2 cases */, 95|128,2/*351*/, TARGET_VAL(ISD::SHL),// ->41747
21731 /* 41434*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
21756 /* 41495*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::SHL),// ->41571
21802 /* 41592*/ OPC_SwitchOpcode /*2 cases */, 73, TARGET_VAL(ISD::SHL),// ->41669
21845 /* 41684*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
21880 /* 41762*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
21894 /* 41787*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
21931 /* 41868*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
21958 /* 41931*/ /*SwitchOpcode*/ 103|128,2/*359*/, TARGET_VAL(ISD::SHL),// ->42294
21973 /* 41961*/ OPC_SwitchOpcode /*2 cases */, 73, TARGET_VAL(ISD::SHL),// ->42038
22015 /* 42052*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22063 /* 42154*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22089 /* 42216*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::SHL),// ->42292
22135 /* 42313*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22148 /* 42337*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22185 /* 42418*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22218 /* 42494*/ OPC_SwitchOpcode /*2 cases */, 35|128,3/*419*/, TARGET_VAL(ISD::SHL),// ->42918
22240 /* 42537*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22254 /* 42561*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22275 /* 42615*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::SHL),// ->42708
22298 /* 42654*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22331 /* 42729*/ OPC_SwitchOpcode /*2 cases */, 90, TARGET_VAL(ISD::SHL),// ->42823
22354 /* 42769*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22384 /* 42838*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22398 /* 42862*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22429 /* 42933*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22443 /* 42958*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22457 /* 42982*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22490 /* 43056*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22504 /* 43080*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22527 /* 43136*/ /*SwitchOpcode*/ 43|128,3/*427*/, TARGET_VAL(ISD::SHL),// ->43567
22542 /* 43166*/ OPC_SwitchOpcode /*2 cases */, 90, TARGET_VAL(ISD::SHL),// ->43260
22565 /* 43206*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22594 /* 43274*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22609 /* 43299*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22652 /* 43393*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22667 /* 43418*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22688 /* 43472*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::SHL),// ->43565
22711 /* 43511*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22744 /* 43586*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22757 /* 43610*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22772 /* 43635*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22804 /* 43708*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22819 /* 43733*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22846 /* 43793*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
22858 /* 43814*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
24680 /* 47453*/ OPC_SwitchOpcode /*2 cases */, 30, TARGET_VAL(ISD::SHL),// ->47487
24717 /* 47523*/ OPC_SwitchOpcode /*2 cases */, 31, TARGET_VAL(ISD::SHL),// ->47558
24757 /* 47596*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
24774 /* 47626*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
24851 /* 47766*/ /*SwitchOpcode*/ 50, TARGET_VAL(ISD::SHL),// ->47819
24976 /* 47991*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::SHL),// ->48046
25078 /* 48178*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::SHL),// ->48212
25134 /* 48286*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::SHL),// ->48321
26049 /* 50044*/ OPC_SwitchOpcode /*4 cases */, 101, TARGET_VAL(ISD::SHL),// ->50149
26592 /* 51100*/ OPC_SwitchOpcode /*2 cases */, 30, TARGET_VAL(ISD::SHL),// ->51134
26629 /* 51170*/ OPC_SwitchOpcode /*2 cases */, 31, TARGET_VAL(ISD::SHL),// ->51205
26794 /* 51500*/ /*SwitchOpcode*/ 50, TARGET_VAL(ISD::SHL),// ->51553
26919 /* 51725*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::SHL),// ->51780
27021 /* 51912*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::SHL),// ->51946
27077 /* 52020*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::SHL),// ->52055
27101 /* 52063*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
27117 /* 52100*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
29358 /* 56653*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
29381 /* 56692*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
29402 /* 56729*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
29435 /* 56787*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
52298 /* 98639*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
52360 /* 98778*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
53713 /*101459*/ /*SwitchOpcode*/ 50, TARGET_VAL(ISD::SHL),// ->101512
53807 /*101629*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::SHL),// ->101684
53897 /*101790*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::SHL),// ->101811
53935 /*101859*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::SHL),// ->101881
53951 /*101885*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
53963 /*101906*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
55380 /*104548*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
55482 /*104743*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
55582 /*104936*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
55779 /*105365*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
55870 /*105566*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
55992 /*105867*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
56153 /*106204*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
56245 /*106376*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
56339 /*106550*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
56424 /*106733*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
56511 /*106918*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
56573 /*107070*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
59599 /*113872*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
59633 /*113934*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
59690 /*114041*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
59720 /*114095*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
60043 /*114745*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
60166 /*114991*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
60511 /*115641*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
60562 /*115737*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
64256 /*123423*/ /*SwitchOpcode*/ 22, TARGET_VAL(ISD::SHL),// ->123448
64274 /*123452*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
65023 /*125033*/ /*SwitchOpcode*/ 86|128,2/*342*/, TARGET_VAL(ISD::SHL),// ->125379
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 883 /* 1574*/ /*SwitchOpcode*/ 35, TARGET_VAL(ISD::SHL),// ->1612
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 4670 /* 9306*/ /*SwitchOpcode*/ 28, TARGET_VAL(ISD::SHL),// ->9337
gen/lib/Target/Mips/MipsGenDAGISel.inc 1386 /* 2489*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
1474 /* 2639*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
11031 /* 20640*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
11230 /* 21012*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
11431 /* 21386*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
11549 /* 21595*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
11670 /* 21807*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
11748 /* 21944*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
11829 /* 22083*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
11881 /* 22172*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
11936 /* 22264*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
11956 /* 22299*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
11978 /* 22336*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
12014 /* 22399*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
12482 /* 23270*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
12690 /* 23651*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
12895 /* 24033*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
13105 /* 24416*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
13312 /* 24800*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
13440 /* 25019*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
13564 /* 25238*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
13694 /* 25459*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
13821 /* 25681*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
13909 /* 25828*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
13993 /* 25975*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14083 /* 26124*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14169 /* 26271*/ OPC_SwitchOpcode /*2 cases */, 106, TARGET_VAL(ISD::SHL),// ->26381
14242 /* 26391*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14299 /* 26488*/ OPC_SwitchOpcode /*2 cases */, 108, TARGET_VAL(ISD::SHL),// ->26600
14374 /* 26610*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14434 /* 26709*/ OPC_SwitchOpcode /*2 cases */, 41, TARGET_VAL(ISD::SHL),// ->26754
14467 /* 26764*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14491 /* 26805*/ OPC_SwitchOpcode /*2 cases */, 42, TARGET_VAL(ISD::SHL),// ->26851
14525 /* 26861*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14552 /* 26906*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14602 /* 26983*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14623 /* 27019*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14646 /* 27054*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14671 /* 27093*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14691 /* 27128*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14714 /* 27163*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14739 /* 27202*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14759 /* 27237*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14782 /* 27272*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
14999 /* 27675*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::SHL),// ->27710
15044 /* 27765*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
15070 /* 27814*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
16156 /* 29843*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SHL),// ->29923
18447 /* 34547*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18646 /* 34919*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18847 /* 35293*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
18965 /* 35502*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19086 /* 35714*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19164 /* 35851*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19245 /* 35990*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19297 /* 36079*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19352 /* 36171*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19372 /* 36206*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19394 /* 36243*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19430 /* 36306*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
19564 /* 36557*/ /*SwitchOpcode*/ 10|128,8/*1034*/, TARGET_VAL(ISD::SHL),// ->37595
gen/lib/Target/Mips/MipsGenFastISel.inc 3420 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3704 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
3788 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
4000 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc53035 /*114488*/ /*SwitchOpcode*/ 124|128,1/*252*/, TARGET_VAL(ISD::SHL),// ->114744
gen/lib/Target/PowerPC/PPCGenDAGISel.inc 3534 /* 7486*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
3572 /* 7573*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
3612 /* 7663*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
3671 /* 7811*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
3732 /* 7960*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
3780 /* 8084*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
3830 /* 8210*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
3860 /* 8287*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
7189 /* 17252*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
7227 /* 17339*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
7267 /* 17429*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
7326 /* 17577*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
7387 /* 17726*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
7435 /* 17850*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
7485 /* 17976*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
7515 /* 18053*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
27461 /* 66536*/ /*SwitchOpcode*/ 45|128,1/*173*/, TARGET_VAL(ISD::SHL),// ->66713
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3248 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 5467 /* 10106*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
6280 /* 11605*/ /*SwitchOpcode*/ 35|128,1/*163*/, TARGET_VAL(ISD::SHL),// ->11772
gen/lib/Target/Sparc/SparcGenDAGISel.inc 2091 /* 3850*/ /*SwitchOpcode*/ 72, TARGET_VAL(ISD::SHL),// ->3925
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc18011 /* 33443*/ /*SwitchOpcode*/ 29|128,2/*285*/, TARGET_VAL(ISD::SHL),// ->33732
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc17961 /* 34483*/ /*SwitchOpcode*/ 115|128,1/*243*/, TARGET_VAL(ISD::SHL),// ->34730
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1917 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc 543 /* 1028*/ OPC_SwitchOpcode /*16 cases */, 30|128,5/*670*/, TARGET_VAL(ISD::SHL),// ->1703
19436 /* 39176*/ /*SwitchOpcode*/ 28|128,5/*668*/, TARGET_VAL(ISD::SHL),// ->39848
45140 /* 94478*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
45194 /* 94601*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
45366 /* 94979*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
45404 /* 95079*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
47561 /* 99705*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
47615 /* 99828*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
47750 /*100115*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
47788 /*100215*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
gen/lib/Target/X86/X86GenFastISel.inc13524 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
14117 case ISD::SHL: return fastEmit_ISD_SHL_ri(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 60 /* 8*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
72 /* 36*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
91 /* 68*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
176 /* 219*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
216 /* 286*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
424 /* 664*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
452 /* 710*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
577 /* 933*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
1208 /* 1971*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
1847 /* 3238*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::SHL),// ->3272
include/llvm/CodeGen/TargetLowering.h 599 if (OldShiftOpcode == ISD::SHL && CC->isOne())
603 if (XC && NewShiftOpcode == ISD::SHL && XC->isOne())
2301 case ISD::SHL:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1531 case ISD::SHL: return visitSHL(N);
1653 case ISD::SHL:
2424 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2427 DAG.getNode(ISD::SHL, DL, VT,
3390 return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc);
3400 DAG.getNode(ISD::SHL, DL, VT, N0,
3430 DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT));
3439 if (N0.getOpcode() == ISD::SHL &&
3442 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
3453 if (N0.getOpcode() == ISD::SHL &&
3457 } else if (N1.getOpcode() == ISD::SHL &&
3465 return DAG.getNode(ISD::SHL, SDLoc(N), VT, Mul, Sh.getOperand(1));
3841 if (N1.getOpcode() == ISD::SHL) {
3908 if (N1.getOpcode() == ISD::SHL &&
4318 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL ||
4950 if (OuterShift == ISD::SHL)
4953 InnerShift = ISD::SHL;
5341 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
5366 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
5368 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
5448 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
5453 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL)
5474 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) {
5496 if (Opc0 != ISD::SHL)
5502 } else if (Opc == ISD::SHL) {
5598 DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt),
5858 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
5894 (OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) &&
5912 return DAG.getNode(ISD::SHL, DL, ShiftedVT, OppShiftLHS,
5932 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) &&
5933 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV)))
6202 if (RHSShift.getOpcode() == ISD::SHL) {
6235 SDValue LHSBits = DAG.getNode(ISD::SHL, DL, VT, AllOnes, LHSShiftAmt);
6356 case ISD::SHL: {
6975 if ((N0Opcode == ISD::SRL || N0Opcode == ISD::SHL) && N0.hasOneUse()) {
6985 Ones = N0Opcode == ISD::SHL ? Ones.shl(ShiftAmt) : Ones.lshr(ShiftAmt);
7035 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0Opcode == ISD::SHL &&
7161 if (N->getOpcode() != ISD::SHL)
7175 bool IsShiftByConstant = (BinOpLHSVal.getOpcode() == ISD::SHL ||
7308 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT,
7322 return DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, N0C, N1C);
7336 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
7344 if (N0.getOpcode() == ISD::SHL) {
7365 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Sum);
7377 N0.getOperand(0).getOpcode() == ISD::SHL) {
7411 return DAG.getNode(ISD::SHL, DL, VT, Ext, Sum);
7435 NewSHL = DAG.getNode(ISD::SHL, DL, N0Op0.getValueType(), N0Op0, NewSHL);
7451 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
7475 Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
7495 SDValue HiBitsMask = DAG.getNode(ISD::SHL, DL, VT, AllBits, N1);
7508 SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
7509 SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
7519 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
7564 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
7609 if (N0.getOpcode() == ISD::SHL && N1C) {
7648 N0.getOperand(0).getOpcode() == ISD::SHL &&
7805 if (N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
7979 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
7993 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N2);
8288 return DAG.getNode(ISD::SHL, DL, VT, Cond, ShAmtC);
8665 return DAG.getNode(ISD::SHL, DL, VT, ZextCond, ShAmtC);
9173 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) ||
9190 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND)
9920 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
9925 if (N0.getOpcode() == ISD::SHL) {
10277 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
10348 Result = DAG.getNode(ISD::SHL, DL, VT,
10363 Result = DAG.getNode(ISD::SHL, DL, VT, Result, ShiftC);
10625 if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
10626 (!LegalOperations || TLI.isOperationLegal(ISD::SHL, VT)) &&
10627 TLI.isTypeDesirableForOp(ISD::SHL, VT)) {
10640 return DAG.getNode(ISD::SHL, SL, VT, Trunc, Amt);
16433 if (Op1.getOpcode() != ISD::SHL) {
16435 if (Op1.getOpcode() != ISD::SHL)
20070 TLI.isOperationLegal(ISD::SHL, VT) &&
20080 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
20132 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
lib/CodeGen/SelectionDAG/FastISel.cpp 1823 return selectBinaryOp(I, ISD::SHL);
1977 Opcode = ISD::SHL;
1987 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 811 ISD::SHL, dl, Hi.getValueType(), Hi,
842 ISD::SHL, dl, Hi.getValueType(), Hi,
1171 case ISD::SHL:
1547 SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst);
2564 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT));
2571 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT));
2578 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT));
2587 DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2612 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2613 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2623 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2624 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2625 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2626 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2879 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3268 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3307 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3316 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3415 ISD::SHL, dl, PairTy, Tmp2,
3454 ISD::SHL, dl, Index.getValueType(), Index,
3660 case ISD::SHL: {
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 271 ISD::SHL, dl, RVT, DAG.getConstant(1, dl, RVT),
288 DAG.getNode(ISD::SHL, dl, LVT, SignBit,
296 ISD::SHL, dl, LVT, DAG.getConstant(1, dl, LVT),
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 84 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
692 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
694 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
753 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
854 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
1116 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
1194 case ISD::SHL:
1341 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1775 case ISD::SHL:
1844 if (N->getOpcode() == ISD::SHL) {
1849 Hi = DAG.getNode(ISD::SHL, DL,
1855 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1857 DAG.getNode(ISD::SHL, DL, NVT, InH,
1879 DAG.getNode(ISD::SHL, DL, NVT, InH,
1903 DAG.getNode(ISD::SHL, DL, NVT, InH,
1944 case ISD::SHL:
1946 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1972 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1972 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1974 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1978 if (N->getOpcode() != ISD::SHL)
1990 if (N->getOpcode() != ISD::SHL)
2026 case ISD::SHL:
2028 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
2030 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
2035 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
2048 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2063 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2741 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2832 DAG.getNode(ISD::SHL, dl, NVT, V, Shift));
3170 if (N->getOpcode() == ISD::SHL) {
3214 if (N->getOpcode() == ISD::SHL) {
3616 case ISD::SHL:
3948 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp 972 Hi = DAG.getNode(ISD::SHL, dlHi, NVT, Hi,
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 378 case ISD::SHL:
716 DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
735 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
947 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
958 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
1017 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
1107 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) &&
1122 if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) ||
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 141 case ISD::SHL:
948 case ISD::SHL:
2821 case ISD::SHL:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2795 case ISD::SHL:
3371 if (Val.getOpcode() == ISD::SHL) {
3566 case ISD::SHL:
4703 case ISD::SHL: return std::make_pair(C1 << C2, true);
5136 case ISD::SHL:
9154 case ISD::SHL:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 258 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
2707 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
3165 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
3923 IdxN = DAG.getNode(ISD::SHL, dl,
4909 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
6264 SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : NShAmt);
6273 SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : InvShAmt);
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 689 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 239 case ISD::SHL: return "shl";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 1273 case ISD::SHL: {
1296 unsigned Opc = ISD::SHL;
1328 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1333 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1357 Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA));
1395 if (Op0.getOpcode() == ISD::SHL) {
1406 Opc = ISD::SHL;
1562 TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt));
1851 TLO.DAG.getNode(ISD::SHL, dl, VT, Sign, ShAmt));
2499 case ISD::SHL:
2927 SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt);
2957 case ISD::SHL:
2961 NewShiftOpcode = ISD::SHL;
3042 SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One);
5710 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
5789 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||
5818 SDValue ShX = DAG.getNode(ISD::SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt);
5854 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||
5867 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL;
5868 unsigned HsOpc = IsLeft ? ISD::SRL : ISD::SHL;
5931 DAG.getNode(ISD::SHL, dl, DstVT, R,
6427 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount);
6606 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
7189 Result = DAG.getNode(ISD::SHL, dl, VT, LHS, ShiftAmt);
lib/CodeGen/SwitchLoweringUtils.cpp 281 if (!TLI->isOperationLegal(ISD::SHL, PTy))
lib/CodeGen/TargetLoweringBase.cpp 1604 case Shl: return ISD::SHL;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 363 case ISD::SHL:
377 assert(V.getOpcode() == ISD::SHL && "invalid opcode");
406 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::SHL &&
412 if (LHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(LHS))
414 if (RHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(RHS))
654 if (N.getOpcode() == ISD::SHL) {
887 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
944 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
952 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
1057 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
1065 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
1726 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, ShlImm)) {
2162 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SHL, ShlImm))
2500 case ISD::SHL:
2922 case ISD::SHL:
lib/Target/AArch64/AArch64ISelLowering.cpp 848 setOperationAction(ISD::SHL, VT, Custom);
1957 if (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA)
3042 case ISD::SHL:
3889 Arg = DAG.getNode(ISD::SHL, DL, VA.getLocVT(), Arg,
4208 Arg = DAG.getNode(ISD::SHL, DL, VA.getLocVT(), Arg,
4636 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
5610 SDValue HiBitsForLo = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5678 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5682 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5693 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8015 case ISD::SHL:
8307 Size = DAG.getNode(ISD::SHL, dl, MVT::i64, Size,
8479 Base.getOperand(1).getOpcode() == ISD::SHL &&
9457 SDValue ShiftedVal = DAG.getNode(ISD::SHL, DL, VT, N0,
9470 return DAG.getNode(ISD::SHL, DL, VT, Res,
9708 if (N.getOpcode() == ISD::SHL)
11440 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
11502 case ISD::SHL:
12357 return X.getValueType().isScalarInteger() || NewShiftOpcode == ISD::SHL;
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 1979 } else if (N->getOperand(0).getOpcode() == ISD::SHL) {
1985 if (N->getOperand(0).getOpcode() == ISD::SHL) {
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 370 setOperationAction(ISD::SHL, VT, Expand);
490 setTargetDAGCombine(ISD::SHL);
1822 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
2439 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
2449 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
2634 DAG.getNode(ISD::SHL, DL, MVT::i32, E,
2648 SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B);
3054 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0));
3073 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
3220 Src.getOpcode() == ISD::SHL)) {
3939 case ISD::SHL: {
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp 362 case ISD::SHL:
lib/Target/AMDGPU/R600ISelLowering.cpp 812 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
814 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
816 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
847 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
848 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
1188 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1200 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1204 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt);
1289 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1293 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift);
1297 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift);
1417 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
lib/Target/AMDGPU/SIISelLowering.cpp 601 setOperationAction(ISD::SHL, MVT::v2i16, Legal);
624 setOperationAction(ISD::SHL, MVT::v4i16, Custom);
2536 Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y,
2544 Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z,
4067 case ISD::SHL:
4670 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount);
4846 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
4849 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT,
4889 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
4997 SDValue ShlHi = DAG.getNode(ISD::SHL, SL, MVT::i32, Hi,
8081 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
8099 if (Ptr.getOpcode() == ISD::SHL) {
8212 case ISD::SHL:
8268 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(LHS), VT, Ext,
lib/Target/ARC/ARCISelLowering.cpp 101 setOperationAction(ISD::SHL, MVT::i32, Legal);
190 SDValue LS = DAG.getNode(ISD::SHL, dl, MVT::i32, Op0,
lib/Target/ARM/ARMISelDAGToDAG.cpp 423 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
2703 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
lib/Target/ARM/ARMISelLowering.cpp 185 setOperationAction(ISD::SHL, VT, Custom);
253 setOperationAction(ISD::SHL, VT, Custom);
902 setTargetDAGCombine(ISD::SHL);
1057 setOperationAction(ISD::SHL, MVT::i64, Custom);
1425 setTargetDAGCombine(ISD::SHL);
1779 if (Op.getOpcode() != ISD::SHL)
3158 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3642 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
3663 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
4260 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4272 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
5809 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5849 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5854 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5862 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6046 if (N->getOpcode() == ISD::SHL) {
6084 N->getOpcode() == ISD::SHL) &&
6131 if (!isOneConstant(N->getOperand(1)) || N->getOpcode() == ISD::SHL)
9179 case ISD::SHL:
9290 case ISD::SHL:
11588 if (N->getOpcode() != ISD::SHL)
11595 if (N->getOpcode() != ISD::SHL)
11684 if (U->getOperand(0).getOpcode() == ISD::SHL ||
11685 U->getOperand(1).getOpcode() == ISD::SHL)
11695 if (N->getOperand(0).getOpcode() != ISD::SHL)
11732 SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1));
11858 DAG.getNode(ISD::SHL, DL, VT,
11865 DAG.getNode(ISD::SHL, DL, VT,
11878 DAG.getNode(ISD::SHL, DL, VT,
11886 DAG.getNode(ISD::SHL, DL, VT,
11897 Res = DAG.getNode(ISD::SHL, DL, VT,
11928 if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL)
11931 bool LeftShift = N0->getOpcode() == ISD::SHL;
11959 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
11972 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL,
11983 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
11998 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL,
12069 if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) {
12222 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
13759 if (ST->isThumb1Only() && N->getOpcode() == ISD::SHL && VT == MVT::i32 &&
13784 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
13805 case ISD::SHL:
14395 Res = DAG.getNode(ISD::SHL, dl, VT, Res,
14449 case ISD::SHL:
14830 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM))
lib/Target/ARM/ARMSelectionDAGInfo.h 26 case ISD::SHL: return ARM_AM::lsl;
lib/Target/AVR/AVRISelLowering.cpp 82 setOperationAction(ISD::SHL, MVT::i8, Custom);
85 setOperationAction(ISD::SHL, MVT::i16, Custom);
291 case ISD::SHL:
325 case ISD::SHL:
687 case ISD::SHL:
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 602 if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL)
883 case ISD::SHL: return SelectSHL(N);
1046 if (T1.getOpcode() != ISD::SHL)
1071 SDValue NewShl = DAG.getNode(ISD::SHL, DL, VT, NewAdd, C);
1147 SDValue NewShl = DAG.getNode(ISD::SHL, dl, VT, NewSrl, DC);
1605 case ISD::SHL:
1732 if (Val.getOpcode() != ISD::SHL ||
1799 if (Val.getOpcode() == ISD::SHL) {
1818 } else if (V.getOpcode() == ISD::SHL) {
1839 } else if (V.getOpcode() == ISD::SHL) {
1930 if (NOpcode == ISD::SHL)
1942 ((isOpcodeHandled(Op0.getNode()) && Op0.getOpcode() == ISD::SHL &&
1944 (isOpcodeHandled(Op1.getNode()) && Op1.getOpcode() == ISD::SHL &&
1978 (Child.getOpcode() == ISD::MUL || Child.getOpcode() == ISD::SHL) &&
2014 (NOpcode == ISD::MUL && ChildOpcode == ISD::SHL));
2018 if (ChildOpcode == ISD::SHL)
2057 SDValue New = CurDAG->getNode(ISD::SHL, SDLoc(N), Mul1.Value.getValueType(),
2177 ISD::SHL, SDLoc(V0), VT, V0,
2207 ISD::SHL, SDLoc(NewRoot), VT, V0,
lib/Target/Hexagon/HexagonISelLowering.cpp 1463 setOperationAction(ISD::SHL, VT, Custom);
2043 case ISD::SHL:
2190 SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2191 SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
2859 case ISD::SHL:
2907 case ISD::SHL:
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 108 setOperationAction(ISD::SHL, T, Custom);
160 setOperationAction(ISD::SHL, T, Custom);
291 return DAG.getNode(ISD::SHL, dl, MVT::i32,
1542 case ISD::SHL:
1568 case ISD::SHL:
lib/Target/Lanai/LanaiAluCode.h 134 case ISD::SHL:
lib/Target/Lanai/LanaiISelLowering.cpp 946 Res = DAG.getNode(ISD::SHL, DL, VT, V,
960 DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
1264 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1268 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1276 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1315 DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
lib/Target/MSP430/MSP430ISelLowering.cpp 72 setOperationAction(ISD::SHL, MVT::i8, Custom);
75 setOperationAction(ISD::SHL, MVT::i16, Custom);
337 case ISD::SHL: // FALLTHROUGH
964 case ISD::SHL:
990 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
lib/Target/Mips/MipsISelLowering.cpp 508 setTargetDAGCombine(ISD::SHL);
822 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
888 And1.getOperand(0).getOpcode() == ISD::SHL) {
1174 case ISD::SHL:
2234 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2237 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2284 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2294 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2328 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2359 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2470 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2472 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2505 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2507 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2610 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
3203 ISD::SHL, DL, VA.getLocVT(), Arg,
3707 ISD::SHL, DL, VA.getLocVT(), Val,
4289 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
lib/Target/Mips/MipsISelLowering.h 473 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
476 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
lib/Target/Mips/MipsSEISelLowering.cpp 101 setTargetDAGCombine(ISD::SHL);
340 setOperationAction(ISD::SHL, Ty, Legal);
804 return DAG.getNode(ISD::SHL, DL, VT, X,
905 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
1038 case ISD::SHL:
1500 Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1524 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));
1659 DAG.getNode(ISD::SHL, DL, VecTy, One,
1695 DAG.getNode(ISD::SHL, DL, VecTy, One,
1993 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
2176 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2182 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 3494 } else if (LHS->getOpcode() == ISD::SHL) {
lib/Target/NVPTX/NVPTXISelLowering.cpp 521 setTargetDAGCombine(ISD::SHL);
2002 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2042 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2059 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2064 SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2069 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4662 if (N->getOpcode() == ISD::SHL) {
4765 case ISD::SHL:
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 601 if (Opcode == ISD::SHL) {
735 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
737 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
744 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
745 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
755 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
758 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
768 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
773 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
1239 case ISD::SHL:
3660 case ISD::SHL:
4755 case ISD::SHL: {
lib/Target/PowerPC/PPCISelLowering.cpp 801 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
809 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
816 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
877 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1110 setTargetDAGCombine(ISD::SHL);
6112 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
12575 DAG.getNode(ISD::SHL, dl, N->getValueType(0), N->getOperand(0), ShiftCst),
13372 case ISD::SHL:
15112 case ISD::SHL:
15375 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
15392 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
lib/Target/RISCV/RISCVISelLowering.cpp 105 setOperationAction(ISD::SHL, MVT::i32, Custom);
743 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
747 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
749 SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusXLen);
794 SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
796 DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, XLenMinus1Shamt);
818 case ISD::SHL:
889 case ISD::SHL:
lib/Target/Sparc/SparcISelLowering.cpp 340 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
1195 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1983 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32));
1992 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32));
2922 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 877 case ISD::SHL: {
1519 case ISD::SHL:
1872 Result = CurDAG->getNode(ISD::SHL, DL, VT, Result,
lib/Target/SystemZ/SystemZISelLowering.cpp 364 setOperationAction(ISD::SHL, VT, Custom);
2185 if (C.Op0.getOpcode() == ISD::SHL &&
2388 NewC.Op0.getOpcode() == ISD::SHL &&
2920 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
3132 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
3605 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
3699 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3714 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
3815 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
5032 case ISD::SHL:
5466 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
5474 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
6007 if (SHL->getOpcode() != ISD::SHL)
lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp 172 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM,
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 146 for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL}) {
1014 case ISD::SHL:
1534 case ISD::SHL:
lib/Target/X86/X86ISelDAGToDAG.cpp 664 if (U->getOperand(0).getOpcode() == ISD::SHL &&
668 if (U->getOperand(1).getOpcode() == ISD::SHL &&
690 case ISD::SHL:
828 case ISD::SHL:
839 case ISD::SHL: NewOpc = X86ISD::VSHLV; break;
1587 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
1630 if (Shift.getOpcode() != ISD::SHL ||
1657 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
1767 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
1824 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewAnd, NewSHLAmt);
1911 case ISD::SHL:
2138 if (N.getOperand(0).getOpcode() != ISD::SHL || !N.getOperand(0).hasOneUse())
2158 SDValue NewShl = CurDAG->getNode(ISD::SHL, DL, VT, Zext, Shl.getOperand(1));
3235 if (M0->getOpcode() != ISD::SHL || !checkOneUse(M0))
3261 if (M0->getOpcode() != ISD::SHL || !checkOneUse(M0))
3317 if (N0->getOpcode() != ISD::SHL || !checkOneUse(N0))
3406 SDValue Control = CurDAG->getNode(ISD::SHL, DL, MVT::i32, NBits, C8);
3749 if (Shift.getOpcode() != ISD::SHL || !Shift.hasOneUse())
3828 SDValue NewSHL = CurDAG->getNode(ISD::SHL, dl, NVT, NewBinOp,
4473 case ISD::SHL:
lib/Target/X86/X86ISelLowering.cpp 1001 setOperationAction(ISD::SHL, VT, Custom);
1135 setOperationAction(ISD::SHL, VT, Custom);
1456 setOperationAction(ISD::SHL, VT, Custom);
1672 setOperationAction(ISD::SHL, VT, Custom);
1846 setTargetDAGCombine(ISD::SHL);
5110 return NewShiftOpcode == ISD::SHL;
5115 assert(((N->getOpcode() == ISD::SHL &&
5118 N->getOperand(0).getOpcode() == ISD::SHL)) &&
7489 NextElt = DAG.getNode(ISD::SHL, dl, MVT::i32, NextElt,
9205 case ISD::SHL:
18205 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
18250 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
19308 In = DAG.getNode(ISD::SHL, DL, ExtVT,
19356 In = DAG.getNode(ISD::SHL, DL, InVT, In,
20040 case ISD::SHL:
20375 if (Op1.getOpcode() == ISD::SHL)
20377 if (Op0.getOpcode() == ISD::SHL) {
20767 Result = DAG.getNode(ISD::SHL, dl, VT, Result,
22417 case ISD::SHL:
23833 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
25559 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
25577 if (Op.getOpcode() == ISD::SHL) {
25640 unsigned LogicalOp = (Opcode == ISD::SHL ? ISD::SHL : ISD::SRL);
25640 unsigned LogicalOp = (Opcode == ISD::SHL ? ISD::SHL : ISD::SRL);
25649 if (Opcode != ISD::SHL)
25736 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
25794 if (Opc == ISD::SHL || Opc == ISD::SRL)
25862 (VT == MVT::v4i32 || Subtarget.hasSSE41() || Opc != ISD::SHL ||
25879 if (Opc == ISD::SHL)
26011 Amt = DAG.getNode(ISD::SHL, dl, ExVT, DAG.getConstant(1, dl, ExVT), Amt);
26086 if (Opc == ISD::SHL || Opc == ISD::SRL) {
26349 Amt = DAG.getNode(ISD::SHL, DL, ExtVT, Amt, DAG.getConstant(5, DL, ExtVT));
26356 DAG.getNode(ISD::SHL, DL, VT, R, DAG.getConstant(4, DL, VT)),
26366 DAG.getNode(ISD::SHL, DL, VT, R, DAG.getConstant(2, DL, VT)),
26376 DAG.getNode(ISD::SHL, DL, VT, R, DAG.getConstant(1, DL, VT)),
26386 bool LegalVarShifts = SupportedVectorVarShift(VT, Subtarget, ISD::SHL) &&
26394 SDValue SHL = DAG.getNode(ISD::SHL, DL, VT, R, Amt);
26739 Hi = DAG.getNode(ISD::SHL, DL, MVT::i64, Hi,
26748 Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
26896 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), ShifterV);
27753 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
37624 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
37936 Result = DAG.getNode(ISD::SHL, DL, VT, Result,
38005 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
38007 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
38186 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
38193 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
38215 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
38224 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
38234 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
38241 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
38329 N0.getOpcode() != ISD::SHL || !N0.hasOneUse() ||
38355 return DAG.getNode(ISD::SHL, DL, VT, NN,
38931 if (ShiftedIndex.getOpcode() != ISD::SHL)
39660 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
39662 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
39744 unsigned InnerShift = (ISD::FSHL == Opc ? ISD::SRL : ISD::SHL);
39756 if (InnerShift == ISD::SHL && Op1.getOpcode() == ISD::ADD &&
42239 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
43371 if ((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) &&
44921 case ISD::SHL: return combineShiftLeft(N, DAG);
45044 if (Opc == ISD::SHL && VT.isVector() && VT.getVectorElementType() == MVT::i8)
45055 if ((Opc == ISD::MUL || Opc == ISD::SHL) && VT == MVT::i8)
45068 case ISD::SHL:
45144 case ISD::SHL:
lib/Target/X86/X86TargetTransformInfo.cpp 290 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand.
316 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand.
331 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand.
335 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split.
450 { ISD::SHL, MVT::v16i16, 1 }, // psllw.
465 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
466 { ISD::SHL, MVT::v4i32, 1 }, // pslld
467 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
497 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw
501 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw
505 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw
509 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence.
524 { ISD::SHL, MVT::v16i32, 1 },
528 { ISD::SHL, MVT::v8i64, 1 },
558 { ISD::SHL, MVT::v4i32, 1 },
561 { ISD::SHL, MVT::v8i32, 1 },
564 { ISD::SHL, MVT::v2i64, 1 },
566 { ISD::SHL, MVT::v4i64, 1 },
572 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
587 { ISD::SHL, MVT::v16i8, 1 },
590 { ISD::SHL, MVT::v8i16, 1 },
593 { ISD::SHL, MVT::v4i32, 1 },
596 { ISD::SHL, MVT::v2i64, 1 },
600 { ISD::SHL, MVT::v32i8, 2+2 },
603 { ISD::SHL, MVT::v16i16, 2+2 },
606 { ISD::SHL, MVT::v8i32, 2+2 },
609 { ISD::SHL, MVT::v4i64, 2+2 },
622 ShiftISD = ISD::SHL;
630 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split.
631 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split.
632 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split.
657 if (ISD == ISD::SHL &&
668 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence.
669 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
777 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence.
778 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split.
779 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence.
780 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
781 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld
782 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split
808 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence.
809 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence.
810 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
811 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence.
812 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split.
lib/Target/XCore/XCoreISelLowering.cpp 360 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
395 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
455 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,