|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc50808 /*109446*/ OPC_CheckChild2CondCode, ISD::SETULT,
51310 /*110815*/ OPC_CheckChild2CondCode, ISD::SETULT,
51812 /*112184*/ OPC_CheckChild2CondCode, ISD::SETULT,
52000 /*112651*/ OPC_CheckChild2CondCode, ISD::SETULT,
52260 /*113274*/ OPC_CheckChild2CondCode, ISD::SETULT,
52520 /*113897*/ OPC_CheckChild2CondCode, ISD::SETULT,
60397 /*132135*/ OPC_CheckChild2CondCode, ISD::SETULT,
60528 /*132373*/ OPC_CheckChild2CondCode, ISD::SETULT,
60791 /*132853*/ OPC_CheckChild2CondCode, ISD::SETULT,
61041 /*133392*/ OPC_CheckChild2CondCode, ISD::SETULT,
61498 /*134489*/ OPC_CheckChild2CondCode, ISD::SETULT,
61970 /*135616*/ OPC_CheckChild2CondCode, ISD::SETULT,
62212 /*136144*/ OPC_CheckChild2CondCode, ISD::SETULT,
gen/lib/Target/BPF/BPFGenDAGISel.inc 2070 return (N->getZExtValue() == ISD::SETULT);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc29087 /* 56132*/ OPC_CheckChild2CondCode, ISD::SETULT,
29107 /* 56173*/ OPC_CheckChild2CondCode, ISD::SETULT,
29176 /* 56308*/ OPC_CheckChild2CondCode, ISD::SETULT,
29219 /* 56391*/ OPC_CheckChild2CondCode, ISD::SETULT,
29725 /* 57363*/ OPC_CheckChild2CondCode, ISD::SETULT,
29808 /* 57521*/ OPC_CheckChild2CondCode, ISD::SETULT,
29883 /* 57675*/ OPC_CheckChild2CondCode, ISD::SETULT,
29952 /* 57819*/ OPC_CheckChild2CondCode, ISD::SETULT,
29984 /* 57879*/ OPC_CheckChild2CondCode, ISD::SETULT,
30060 /* 58035*/ OPC_CheckChild2CondCode, ISD::SETULT,
30092 /* 58095*/ OPC_CheckChild2CondCode, ISD::SETULT,
30168 /* 58251*/ OPC_CheckChild2CondCode, ISD::SETULT,
30200 /* 58311*/ OPC_CheckChild2CondCode, ISD::SETULT,
30388 /* 58716*/ OPC_CheckChild2CondCode, ISD::SETULT,
30543 /* 59062*/ OPC_CheckChild2CondCode, ISD::SETULT,
31025 /* 59918*/ OPC_CheckChild2CondCode, ISD::SETULT,
51614 /* 97238*/ OPC_CheckChild2CondCode, ISD::SETULT,
51770 /* 97517*/ OPC_CheckChild2CondCode, ISD::SETULT,
52083 /* 98164*/ OPC_CheckChild2CondCode, ISD::SETULT,
52097 /* 98192*/ OPC_CheckChild2CondCode, ISD::SETULT,
52281 /* 98597*/ OPC_CheckChild2CondCode, ISD::SETULT,
gen/lib/Target/Mips/MipsGenDAGISel.inc16562 /* 30746*/ OPC_CheckChild2CondCode, ISD::SETULT,
16578 /* 30776*/ OPC_CheckChild2CondCode, ISD::SETULT,
16638 /* 30910*/ OPC_CheckChild2CondCode, ISD::SETULT,
16655 /* 30941*/ OPC_CheckChild2CondCode, ISD::SETULT,
16687 /* 31001*/ OPC_CheckChild2CondCode, ISD::SETULT,
16867 /* 31403*/ OPC_CheckChild2CondCode, ISD::SETULT,
16991 /* 31686*/ OPC_CheckChild2CondCode, ISD::SETULT,
17030 /* 31769*/ OPC_CheckChild2CondCode, ISD::SETULT,
17154 /* 32033*/ OPC_CheckChild2CondCode, ISD::SETULT,
17238 /* 32189*/ OPC_CheckChild2CondCode, ISD::SETULT,
17407 /* 32546*/ OPC_CheckChild2CondCode, ISD::SETULT,
17491 /* 32702*/ OPC_CheckChild2CondCode, ISD::SETULT,
17664 /* 33071*/ OPC_CheckChild2CondCode, ISD::SETULT,
17700 /* 33139*/ OPC_CheckChild2CondCode, ISD::SETULT,
17744 /* 33225*/ OPC_CheckChild2CondCode, ISD::SETULT,
17780 /* 33293*/ OPC_CheckChild2CondCode, ISD::SETULT,
17824 /* 33379*/ OPC_CheckChild2CondCode, ISD::SETULT,
17860 /* 33447*/ OPC_CheckChild2CondCode, ISD::SETULT,
17904 /* 33533*/ OPC_CheckChild2CondCode, ISD::SETULT,
17940 /* 33601*/ OPC_CheckChild2CondCode, ISD::SETULT,
18001 /* 33714*/ OPC_CheckChild2CondCode, ISD::SETULT,
18104 /* 33905*/ OPC_CheckChild2CondCode, ISD::SETULT,
29399 /* 55631*/ OPC_CheckCondCode, ISD::SETULT,
29584 /* 56192*/ OPC_CheckChild2CondCode, ISD::SETULT,
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc59928 /*126970*/ OPC_CheckChild2CondCode, ISD::SETULT,
59942 /*126997*/ OPC_CheckChild2CondCode, ISD::SETULT,
59956 /*127024*/ OPC_CheckChild2CondCode, ISD::SETULT,
59970 /*127051*/ OPC_CheckChild2CondCode, ISD::SETULT,
59984 /*127078*/ OPC_CheckChild2CondCode, ISD::SETULT,
59998 /*127105*/ OPC_CheckChild2CondCode, ISD::SETULT,
60012 /*127132*/ OPC_CheckChild2CondCode, ISD::SETULT,
60026 /*127159*/ OPC_CheckChild2CondCode, ISD::SETULT,
60040 /*127186*/ OPC_CheckChild2CondCode, ISD::SETULT,
60054 /*127213*/ OPC_CheckChild2CondCode, ISD::SETULT,
60068 /*127240*/ OPC_CheckChild2CondCode, ISD::SETULT,
60082 /*127267*/ OPC_CheckChild2CondCode, ISD::SETULT,
61832 /*130690*/ OPC_CheckChild2CondCode, ISD::SETULT,
61856 /*130738*/ OPC_CheckChild2CondCode, ISD::SETULT,
61880 /*130786*/ OPC_CheckChild2CondCode, ISD::SETULT,
61894 /*130813*/ OPC_CheckChild2CondCode, ISD::SETULT,
61908 /*130840*/ OPC_CheckChild2CondCode, ISD::SETULT,
61932 /*130888*/ OPC_CheckChild2CondCode, ISD::SETULT,
61956 /*130936*/ OPC_CheckChild2CondCode, ISD::SETULT,
61970 /*130963*/ OPC_CheckChild2CondCode, ISD::SETULT,
64620 /*136382*/ OPC_CheckChild2CondCode, ISD::SETULT,
64649 /*136446*/ OPC_CheckChild2CondCode, ISD::SETULT,
64678 /*136510*/ OPC_CheckChild2CondCode, ISD::SETULT,
64707 /*136574*/ OPC_CheckChild2CondCode, ISD::SETULT,
66231 /*139939*/ OPC_CheckChild2CondCode, ISD::SETULT,
66415 /*140342*/ OPC_CheckChild2CondCode, ISD::SETULT,
66599 /*140745*/ OPC_CheckChild2CondCode, ISD::SETULT,
66978 /*141583*/ OPC_CheckChild2CondCode, ISD::SETULT,
67668 /*143062*/ OPC_CheckChild2CondCode, ISD::SETULT,
68206 /*144223*/ OPC_CheckChild2CondCode, ISD::SETULT,
gen/lib/Target/PowerPC/PPCGenDAGISel.inc25128 /* 60508*/ OPC_CheckChild2CondCode, ISD::SETULT,
25375 /* 61154*/ OPC_CheckChild2CondCode, ISD::SETULT,
25519 /* 61546*/ OPC_CheckChild2CondCode, ISD::SETULT,
25769 /* 62197*/ OPC_CheckChild2CondCode, ISD::SETULT,
25915 /* 62591*/ OPC_CheckChild2CondCode, ISD::SETULT,
27013 /* 65523*/ OPC_CheckChild2CondCode, ISD::SETULT,
27223 /* 66052*/ OPC_CheckChild2CondCode, ISD::SETULT,
28721 /* 68956*/ OPC_CheckCondCode, ISD::SETULT,
28875 /* 69393*/ OPC_CheckCondCode, ISD::SETULT,
28975 /* 69623*/ OPC_CheckCondCode, ISD::SETULT,
29076 /* 69855*/ OPC_CheckCondCode, ISD::SETULT,
29186 /* 70105*/ OPC_CheckCondCode, ISD::SETULT,
29296 /* 70355*/ OPC_CheckCondCode, ISD::SETULT,
29406 /* 70605*/ OPC_CheckCondCode, ISD::SETULT,
29516 /* 70855*/ OPC_CheckCondCode, ISD::SETULT,
29626 /* 71105*/ OPC_CheckCondCode, ISD::SETULT,
29735 /* 71353*/ OPC_CheckCondCode, ISD::SETULT,
29836 /* 71585*/ OPC_CheckCondCode, ISD::SETULT,
29945 /* 71833*/ OPC_CheckCondCode, ISD::SETULT,
30046 /* 72065*/ OPC_CheckCondCode, ISD::SETULT,
30156 /* 72315*/ OPC_CheckCondCode, ISD::SETULT,
30266 /* 72565*/ OPC_CheckCondCode, ISD::SETULT,
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 6743 /* 12432*/ OPC_CheckChild2CondCode, ISD::SETULT,
6819 /* 12591*/ OPC_CheckChild2CondCode, ISD::SETULT,
7030 /* 13042*/ OPC_CheckChild2CondCode, ISD::SETULT,
7069 /* 13125*/ OPC_CheckChild2CondCode, ISD::SETULT,
7761 /* 14563*/ OPC_CheckChild2CondCode, ISD::SETULT,
7943 /* 14859*/ OPC_CheckChild2CondCode, ISD::SETULT,
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 7609 /* 14112*/ OPC_CheckChild2CondCode, ISD::SETULT,
7682 /* 14244*/ OPC_CheckChild2CondCode, ISD::SETULT,
7903 /* 14648*/ OPC_CheckChild2CondCode, ISD::SETULT,
7977 /* 14786*/ OPC_CheckChild2CondCode, ISD::SETULT,
8052 /* 14927*/ OPC_CheckChild2CondCode, ISD::SETULT,
gen/lib/Target/XCore/XCoreGenDAGISel.inc 1789 /* 3105*/ OPC_CheckChild2CondCode, ISD::SETULT,
include/llvm/CodeGen/ISDOpcodes.h 1060 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
lib/CodeGen/Analysis.cpp 215 case FCmpInst::FCMP_ULT: return ISD::SETULT;
227 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT;
247 case ICmpInst::ICMP_ULT: return ISD::SETULT;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 8144 case ISD::SETULT:
12290 case ISD::SETULT:
19743 CC == ISD::SETULT || CC == ISD::SETLT)) {
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1690 case ISD::SETULT:
3099 case ISD::UMIN: Pred = ISD::SETULT; break;
3359 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 1277 case ISD::SETULT:
2018 Amt, NVBitsNode, ISD::SETULT);
2088 return std::make_pair(ISD::SETULT, ISD::UMIN);
2218 ISD::SETULT);
2230 ISD::SETULT);
2239 LoOps[0], LoOps[1], ISD::SETULT);
2312 Cond = ISD::SETULT;
3043 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT);
3687 case ISD::SETULT: LowCC = ISD::SETULT; break;
3687 case ISD::SETULT: LowCC = ISD::SETULT; break;
3757 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 380 case ISD::SETULT:
423 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE
2023 case ISD::SETULT: return getBoolConstant(C1.ult(C2), dl, VT, OpVT);
2083 case ISD::SETULT: return getBoolConstant(R==APFloat::cmpUnordered ||
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 411 case ISD::SETULT: return "setult";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 354 case ISD::SETULT:
2872 if (Cond == ISD::CondCode::SETULT) {
3120 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
3124 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
3306 case ISD::SETULT:
3329 case ISD::SETULT:
3528 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
3540 if (Cond == ISD::SETLT || Cond == ISD::SETULT) {
3596 if (Cond == ISD::SETULT &&
3663 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
3676 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3745 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
3746 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
3748 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
3892 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
7126 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
lib/Target/AArch64/AArch64ISelLowering.cpp 1448 case ISD::SETULT:
1502 case ISD::SETULT:
1567 case ISD::SETULT:
1992 case ISD::SETULT:
1997 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2019 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1284 case ISD::SETULT: {
lib/Target/AMDGPU/R600ISelLowering.cpp 132 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
138 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
819 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
820 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
857 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
858 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
lib/Target/AMDGPU/SIISelLowering.cpp 9796 (CC == ISD::SETNE || CC == ISD::SETGT || CC == ISD::SETULT)) ||
lib/Target/AMDGPU/SIInsertSkips.cpp 234 case ISD::SETULT:
lib/Target/ARC/ARCISelLowering.cpp 49 case ISD::SETULT:
lib/Target/ARM/ARMISelLowering.cpp 1808 case ISD::SETULT: return ARMCC::LO;
1834 case ISD::SETULT: CondCode = ARMCC::LT; break;
4197 case ISD::SETULT:
4200 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4214 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4620 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
4626 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
4637 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
6233 case ISD::SETULT: Invert = true; Opc = ARMCC::GE; break;
6274 case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH;
14126 (CC == ISD::SETULT && Imm == 1);
lib/Target/AVR/AVRISelLowering.cpp 436 case ISD::SETULT:
530 CC = ISD::SETULT;
lib/Target/BPF/BPFISelLowering.cpp 488 case ISD::SETULT:
694 SET_NEWCC(SETULT, JULT);
lib/Target/Hexagon/HexagonISelLowering.cpp 1512 setCondCodeAction(ISD::SETULT, VT, Expand);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 121 setCondCodeAction(ISD::SETULT, T, Expand);
lib/Target/Lanai/LanaiISelLowering.cpp 828 case ISD::SETULT:
lib/Target/MSP430/MSP430ISelLowering.cpp 1067 case ISD::SETULT:
lib/Target/Mips/MipsISelLowering.cpp 618 case ISD::SETULT: return Mips::FCOND_ULT;
lib/Target/Mips/MipsSEISelLowering.cpp 959 case ISD::SETULT:
1766 Op->getOperand(2), ISD::SETULT);
1772 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1855 Op->getOperand(2), ISD::SETULT);
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 564 case ISD::SETULT:
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 3044 case ISD::SETULT: {
3217 case ISD::SETULT: {
3373 case ISD::SETULT: {
3536 case ISD::SETULT: {
3785 case ISD::SETULT:
3812 case ISD::SETULT:
3858 case ISD::SETULT: return PPC::PRED_LT;
3890 case ISD::SETULT: return 0;
3911 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
3919 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
3955 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
4277 if (InnerCC == ISD::SETULT || InnerCC == ISD::SETUGT) {
4279 InnerCC = (InnerCC == ISD::SETULT) ? ISD::SETLT : ISD::SETGT;
4305 case ISD::SETULT:
5320 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
lib/Target/PowerPC/PPCISelLowering.cpp 487 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
488 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
892 setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
7281 case ISD::SETULT:
7317 case ISD::SETULT:
12001 case ISD::SETULT:
15548 case ISD::SETULT:
lib/Target/RISCV/RISCVISelLowering.cpp 145 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT,
361 case ISD::SETULT:
lib/Target/Sparc/SparcISelLowering.cpp 1373 case ISD::SETULT: return SPCC::ICC_CS;
1397 case ISD::SETULT: return SPCC::FCC_UL;
lib/Target/SystemZ/SystemZISelLowering.cpp 1947 CONV(LT);
2460 else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 89 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
lib/Target/X86/X86ISelLowering.cpp 4675 case ISD::SETULT: return X86::COND_B;
4749 case ISD::SETULT:
20475 case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH;
20587 case ISD::SETULT: {
20720 case ISD::SETULT:
20813 if (Cond == ISD::SETULT) {
20826 case ISD::SETULT: Invert = true; LLVM_FALLTHROUGH;
20849 bool Swap = Cond == ISD::SETLT || Cond == ISD::SETULT ||
25009 case ISD::UMIN: CC = ISD::CondCode::SETULT; break;
36848 case ISD::SETULT:
36948 case ISD::SETULT:
lib/Target/X86/X86InstrInfo.cpp 2317 case ISD::SETULT: