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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 4234 /* 17390*/ /*SwitchOpcode*/ 45|128,35/*4525*/, TARGET_VAL(ISD::SELECT_CC),// ->21919
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28697 /* 68897*/ /*SwitchOpcode*/ 49|128,30/*3889*/, TARGET_VAL(ISD::SELECT_CC),// ->72790
include/llvm/CodeGen/SelectionDAG.h 1004 return getNode(ISD::SELECT_CC, DL, True.getValueType(), LHS, RHS, True,
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 816 if (N.getOpcode() != ISD::SELECT_CC ||
1548 case ISD::SELECT_CC: return visitSELECT_CC(N);
6915 case ISD::SELECT_CC:
8492 if (TLI.isOperationLegal(ISD::SELECT_CC, VT) ||
8494 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))) {
8498 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, VT, Cond0, Cond1, N1,
8822 ISD::SELECT_CC, SDLoc(N), N2.getValueType(), SCC.getOperand(0),
12849 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
12860 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
12874 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
12910 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
12920 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
19693 if (SCC.getOpcode() == ISD::SELECT_CC) {
19728 if (TheSelect->getOpcode() == ISD::SELECT_CC) {
19858 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1025 case ISD::SELECT_CC:
1028 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1036 if (Node->getOpcode() == ISD::SELECT_CC)
3542 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3550 case ISD::SELECT_CC: {
3612 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3617 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 101 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break;
761 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
850 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break;
1130 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1655 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break;
1922 case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break;
1983 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
2093 case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break;
2309 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 77 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
813 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
1174 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
1677 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
3608 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp 550 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0),
552 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0),
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 395 case ISD::SELECT_CC:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 62 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
523 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
847 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
2719 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
4045 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2763 case ISD::SELECT_CC:
3596 case ISD::SELECT_CC:
7224 case ISD::SELECT_CC:
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 275 case ISD::SELECT_CC: return "select_cc";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 1227 case ISD::SELECT_CC:
lib/Target/AArch64/AArch64ISelLowering.cpp 212 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
213 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
214 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
215 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
216 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
256 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
398 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
441 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
468 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
685 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
854 setOperationAction(ISD::SELECT_CC, VT, Expand);
2259 if (Sel.getOpcode() != ISD::SELECT_CC)
2261 if (Sel.getOpcode() != ISD::SELECT_CC)
2980 case ISD::SELECT_CC:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 344 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
388 setOperationAction(ISD::SELECT_CC, VT, Expand);
428 setOperationAction(ISD::SELECT_CC, VT, Expand);
498 setTargetDAGCombine(ISD::SELECT_CC);
lib/Target/AMDGPU/R600ISelLowering.cpp 157 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
158 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
278 setTargetDAGCombine(ISD::SELECT_CC);
487 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
993 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
1050 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1074 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1076 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1878 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1886 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0),
1971 case ISD::SELECT_CC: {
1982 if (LHS.getOpcode() != ISD::SELECT_CC) {
lib/Target/AMDGPU/SIISelLowering.cpp 202 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
203 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
204 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
205 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
206 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
461 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
500 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
lib/Target/ARC/ARCISelLowering.cpp 116 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
753 case ISD::SELECT_CC:
lib/Target/ARM/ARMISelLowering.cpp 181 setOperationAction(ISD::SELECT_CC, VT, Expand);
1278 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1279 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1280 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1284 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
4745 if (Op2.getOpcode() != ISD::SELECT_CC)
9158 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
lib/Target/AVR/AVRISelLowering.cpp 102 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
103 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
104 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
105 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
699 case ISD::SELECT_CC:
lib/Target/BPF/BPFISelLowering.cpp 103 setOperationAction(ISD::SELECT_CC, VT, Custom);
196 case ISD::SELECT_CC:
lib/Target/Hexagon/HexagonISelLowering.cpp 1404 setOperationAction(ISD::SELECT_CC, VT, Expand);
1408 setOperationAction(ISD::SELECT_CC, VT, Expand);
1434 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
lib/Target/Lanai/LanaiISelLowering.cpp 90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
190 case ISD::SELECT_CC:
lib/Target/MSP430/MSP430ISelLowering.cpp 92 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
93 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
345 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
lib/Target/Mips/MipsISelLowering.cpp 407 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
408 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
409 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
410 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
lib/Target/Mips/MipsSEISelLowering.cpp 129 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
248 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
252 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
257 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
295 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
lib/Target/NVPTX/NVPTXISelLowering.cpp 398 setOperationAction(ISD::SELECT_CC, VT, Expand);
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 3579 Compare.getOpcode() == ISD::SELECT_CC) &&
3591 int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2;
4210 assert(N->getOpcode() == ISD::SELECT_CC && "Expecting a SELECT_CC here.");
4234 (FalseRes.getOpcode() != ISD::SELECT_CC || CC != ISD::SETEQ)))
4237 bool InnerIsSel = FalseRes.getOpcode() == ISD::SELECT_CC;
4240 SetOrSelCC.getOpcode() != ISD::SELECT_CC)
4807 case ISD::SELECT_CC: {
5268 if (O.getOpcode() != ISD::SELECT_CC)
lib/Target/PowerPC/PPCISelLowering.cpp 360 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
361 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
618 setOperationAction(ISD::SELECT_CC, VT, Promote);
619 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
1139 setTargetDAGCombine(ISD::SELECT_CC);
10142 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
12039 N->getOpcode() == ISD::SELECT_CC) {
12081 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
12088 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
12093 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
12133 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
12146 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
12182 } else if (User->getOpcode() == ISD::SELECT_CC) {
12206 } else if (User->getOpcode() == ISD::SELECT_CC) {
12260 case ISD::SELECT_CC: C = 2; break;
12327 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
12349 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
12359 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
12393 } else if (User->getOpcode() == ISD::SELECT_CC) {
12418 } else if (User->getOpcode() == ISD::SELECT_CC) {
12494 case ISD::SELECT_CC: C = 2; break;
12512 PromOp.getOpcode() == ISD::SELECT_CC) {
12543 PromOp.getOpcode() == ISD::SELECT_CC) {
13405 case ISD::SELECT_CC:
lib/Target/RISCV/RISCVISelLowering.cpp 89 setOperationAction(ISD::SELECT_CC, XLenVT, Expand);
157 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
174 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1543 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1544 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1545 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1546 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1563 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
3029 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
lib/Target/SystemZ/SystemZISelLowering.cpp 140 setOperationAction(ISD::SELECT_CC, VT, Custom);
4934 case ISD::SELECT_CC:
5450 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 166 for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) {
221 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
lib/Target/X86/X86ISelLowering.cpp 323 setOperationAction(ISD::SELECT_CC, VT, Expand);
428 setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand);
783 setOperationAction(ISD::SELECT_CC, VT, Expand);
lib/Target/XCore/XCoreISelLowering.cpp 92 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);