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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc27971 /* 58673*/ /*SwitchOpcode*/ 50, TARGET_VAL(ISD::SELECT),// ->58726
28003 /* 58730*/ OPC_CheckOpcode, TARGET_VAL(ISD::SELECT),
50324 /*108135*/ /*SwitchOpcode*/ 83, TARGET_VAL(ISD::SELECT),// ->108221
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc30815 /* 59571*/ OPC_SwitchOpcode /*3 cases */, 4|128,3/*388*/, TARGET_VAL(ISD::SELECT),// ->59964
51490 /* 97010*/ /*SwitchOpcode*/ 15|128,12/*1551*/, TARGET_VAL(ISD::SELECT),// ->98565
gen/lib/Target/Mips/MipsGenDAGISel.inc 2972 /* 5328*/ /*SwitchOpcode*/ 24|128,58/*7448*/, TARGET_VAL(ISD::SELECT),// ->12780
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc54347 /*116884*/ /*SwitchOpcode*/ 43|128,5/*683*/, TARGET_VAL(ISD::SELECT),// ->117571
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28595 /* 68674*/ /*SwitchOpcode*/ 91|128,1/*219*/, TARGET_VAL(ISD::SELECT),// ->68897
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc12655 /* 24371*/ /*SwitchOpcode*/ 36|128,2/*292*/, TARGET_VAL(ISD::SELECT),// ->24667
gen/lib/Target/XCore/XCoreGenDAGISel.inc 1501 /* 2511*/ /*SwitchOpcode*/ 43|128,2/*299*/, TARGET_VAL(ISD::SELECT),// ->2814
include/llvm/CodeGen/BasicTTIImpl.h 832 if (ISD == ISD::SELECT) {
include/llvm/CodeGen/SelectionDAG.h 996 auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1546 case ISD::SELECT: return visitSELECT(N);
1925 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
1930 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
7180 BinOpLHSVal.getOpcode() == ISD::SELECT;
8381 DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond1, N1, N2, Flags);
8383 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0,
8393 SDValue InnerSelect = DAG.getNode(ISD::SELECT, DL, N1.getValueType(),
8396 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, N1,
8404 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) {
8412 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), And, N1_1,
8417 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Combined, N1_1,
8423 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) {
8431 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Or, N1,
8436 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Combined, N1,
8907 if (N0->getOpcode() == ISD::SELECT) {
10613 if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) {
10614 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
10620 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1);
12272 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) &&
12272 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) &&
12275 if (Select.getOpcode() != ISD::SELECT)
19821 if (TheSelect->getOpcode() == ISD::SELECT) {
20440 ISD::NodeType SelOpcode = VT.isVector() ? ISD::VSELECT : ISD::SELECT;
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3421 case ISD::SELECT:
3563 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
4278 case ISD::SELECT: {
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 100 case ISD::SELECT: R = SoftenFloatRes_SELECT(N); break;
1129 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
2092 case ISD::SELECT: R = PromoteFloatRes_SELECT(N); break;
2299 return DAG.getNode(ISD::SELECT, SDLoc(N), TrueVal->getValueType(0),
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 75 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
1173 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1419 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1676 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 393 case ISD::SELECT:
784 case ISD::SELECT:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 61 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
732 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
846 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
2718 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2751 case ISD::SELECT:
3590 case ISD::SELECT:
4027 case ISD::SELECT:
5499 case ISD::SELECT:
9152 Scalars.push_back(getNode(ISD::SELECT, dl, EltVT, Operands));
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3263 ISD::VSELECT : ISD::SELECT;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 273 case ISD::SELECT: return "select";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 1209 case ISD::SELECT:
6241 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
6293 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
lib/CodeGen/TargetLoweringBase.cpp 1634 case Select: return ISD::SELECT;
lib/Target/AArch64/AArch64ISelLowering.cpp 207 setOperationAction(ISD::SELECT, MVT::i32, Custom);
208 setOperationAction(ISD::SELECT, MVT::i64, Custom);
209 setOperationAction(ISD::SELECT, MVT::f16, Custom);
210 setOperationAction(ISD::SELECT, MVT::f32, Custom);
211 setOperationAction(ISD::SELECT, MVT::f64, Custom);
255 setOperationAction(ISD::SELECT, MVT::f128, Custom);
397 setOperationAction(ISD::SELECT, MVT::f16, Promote);
440 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
467 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
612 setTargetDAGCombine(ISD::SELECT);
684 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
853 setOperationAction(ISD::SELECT, VT, Expand);
2978 case ISD::SELECT:
5802 Estimate = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, DL,
11753 case ISD::SELECT:
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 596 if (ValTy->isVectorTy() && ISD == ISD::SELECT) {
601 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 },
602 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 },
603 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 },
604 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost },
605 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
606 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost }
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 386 setOperationAction(ISD::SELECT, VT, Expand);
438 setOperationAction(ISD::SELECT, MVT::v2f32, Promote);
439 AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32);
441 setOperationAction(ISD::SELECT, MVT::v3f32, Promote);
442 AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32);
444 setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
445 AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
447 setOperationAction(ISD::SELECT, MVT::v5f32, Promote);
448 AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32);
497 setTargetDAGCombine(ISD::SELECT);
561 case ISD::SELECT:
1608 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
2053 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
2116 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2117 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2185 SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);
2223 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2234 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2241 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2242 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2279 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2357 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprHi);
2361 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprLo);
2382 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32,
3469 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond,
3531 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT,
3572 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);
3976 case ISD::SELECT:
lib/Target/AMDGPU/R600ISelLowering.cpp 167 setOperationAction(ISD::SELECT, MVT::i32, Expand);
168 setOperationAction(ISD::SELECT, MVT::f32, Expand);
169 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
170 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 197 setOperationAction(ISD::SELECT, MVT::i1, Promote);
198 setOperationAction(ISD::SELECT, MVT::i64, Custom);
199 setOperationAction(ISD::SELECT, MVT::f64, Promote);
200 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
648 setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
649 setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
656 setOperationAction(ISD::SELECT, MVT::v2i16, Promote);
657 AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);
658 setOperationAction(ISD::SELECT, MVT::v2f16, Promote);
659 AddPromotedToType(ISD::SELECT, MVT::v2f16, MVT::i32);
662 setOperationAction(ISD::SELECT, MVT::v2i16, Custom);
663 setOperationAction(ISD::SELECT, MVT::v2f16, Custom);
670 setOperationAction(ISD::SELECT, VT, Custom);
1381 case ISD::SELECT:
4029 case ISD::SELECT: return LowerSELECT(Op, DAG);
4320 case ISD::SELECT: {
4334 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, SelectVT,
4722 return DAG.getNode(ISD::SELECT, SL, MVT::i32,
4743 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull,
7650 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
8807 case ISD::SELECT: {
9810 LHS.getOpcode() == ISD::SELECT &&
lib/Target/ARM/ARMISelLowering.cpp 180 setOperationAction(ISD::SELECT, VT, Expand);
1275 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1276 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1277 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1283 setOperationAction(ISD::SELECT, MVT::f16, Custom);
9157 case ISD::SELECT: return LowerSELECT(Op, DAG);
10840 case ISD::SELECT: {
10928 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
lib/Target/ARM/ARMTargetTransformInfo.cpp 446 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
449 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
450 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
451 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }
lib/Target/AVR/AVRISelLowering.cpp 110 setOperationAction(ISD::SELECT, MVT::i8, Expand);
111 setOperationAction(ISD::SELECT, MVT::i16, Expand);
lib/Target/BPF/BPFISelLowering.cpp 102 setOperationAction(ISD::SELECT, VT, Expand);
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 990 if (Op.getOpcode() != ISD::SELECT)
1001 if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
1008 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, NewOr, VOp);
1012 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, VOp, NewOr);
1200 SDValue Sel = DAG.getNode(ISD::SELECT, dl, UVT, OpI1, If1, If0);
lib/Target/Hexagon/HexagonISelLowering.cpp 1459 setOperationAction(ISD::SELECT, VT, Promote);
1460 AddPromotedToType(ISD::SELECT, VT, VT32);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 904 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo);
910 IdxV = DAG.getNode(ISD::SELECT, dl, MVT::i32, PickHi, S, IdxV);
911 SingleV = DAG.getNode(ISD::SELECT, dl, SingleTy, PickHi, V1, V0);
951 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo);
lib/Target/Lanai/LanaiISelLowering.cpp 89 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1353 case ISD::SELECT: {
1438 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
lib/Target/MSP430/MSP430ISelLowering.cpp 90 setOperationAction(ISD::SELECT, MVT::i8, Expand);
91 setOperationAction(ISD::SELECT, MVT::i16, Expand);
lib/Target/Mips/MipsISelLowering.cpp 353 setOperationAction(ISD::SELECT, MVT::f32, Custom);
354 setOperationAction(ISD::SELECT, MVT::f64, Custom);
355 setOperationAction(ISD::SELECT, MVT::i32, Custom);
374 setOperationAction(ISD::SELECT, MVT::i64, Custom);
502 setTargetDAGCombine(ISD::SELECT);
715 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
1163 case ISD::SELECT:
1227 case ISD::SELECT: return lowerSELECT(Op, DAG);
2475 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2477 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2526 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2527 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
lib/Target/Mips/MipsSEISelLowering.cpp 130 setOperationAction(ISD::SELECT, MVT::f16, Promote);
247 setOperationAction(ISD::SELECT, MVT::i32, Legal);
251 setOperationAction(ISD::SELECT, MVT::f32, Legal);
256 setOperationAction(ISD::SELECT, MVT::f64, Custom);
294 setOperationAction(ISD::SELECT, MVT::i64, Legal);
467 case ISD::SELECT: return lowerSELECT(Op, DAG);
lib/Target/NVPTX/NVPTXISelLowering.cpp 510 setOperationAction(ISD::SELECT, MVT::i1, Custom);
2010 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
2070 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
2123 RoundedA = DAG.getNode(ISD::SELECT, SL, VT, IsLarge, A, RoundedA);
2129 return DAG.getNode(ISD::SELECT, SL, VT, IsSmall, RoundedAForSmallA, RoundedA);
2154 RoundedA = DAG.getNode(ISD::SELECT, SL, VT, IsSmall,
2166 return DAG.getNode(ISD::SELECT, SL, VT, IsLarge, A, RoundedA);
2199 case ISD::SELECT:
2218 SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 3565 CompareUse->getOpcode() != ISD::SELECT &&
lib/Target/PowerPC/PPCISelLowering.cpp 353 setOperationAction(ISD::SELECT, MVT::i32, Expand);
354 setOperationAction(ISD::SELECT, MVT::i64, Expand);
355 setOperationAction(ISD::SELECT, MVT::f32, Expand);
356 setOperationAction(ISD::SELECT, MVT::f64, Expand);
615 setOperationAction(ISD::SELECT, VT, Promote);
616 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
695 setOperationAction(ISD::SELECT, MVT::v4i32,
906 setOperationAction(ISD::SELECT, MVT::f128, Expand);
945 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
993 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
1031 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
3054 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
3112 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
3119 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
7737 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
7806 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
12080 N->getOperand(0).getOpcode() != ISD::SELECT &&
12092 N->getOperand(1).getOpcode() != ISD::SELECT &&
12131 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
12145 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
12179 if (User->getOpcode() == ISD::SELECT) {
12203 if (User->getOpcode() == ISD::SELECT) {
12259 case ISD::SELECT: C = 1; break;
12326 N->getOperand(0).getOpcode() != ISD::SELECT &&
12347 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
12358 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
12389 if (User->getOpcode() == ISD::SELECT) {
12414 if (User->getOpcode() == ISD::SELECT) {
12493 case ISD::SELECT: C = 1; break;
12511 if (PromOp.getOpcode() == ISD::SELECT ||
12542 if (PromOp.getOpcode() == ISD::SELECT ||
lib/Target/RISCV/RISCVISelLowering.cpp 88 setOperationAction(ISD::SELECT, XLenVT, Custom);
158 setOperationAction(ISD::SELECT, MVT::f32, Custom);
175 setOperationAction(ISD::SELECT, MVT::f64, Custom);
381 case ISD::SELECT:
753 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
754 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
805 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
806 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
lib/Target/Sparc/SparcISelLowering.cpp 1524 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1525 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1526 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1527 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1560 setOperationAction(ISD::SELECT, MVT::i64, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 137 setOperationAction(ISD::SELECT, VT, Expand);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 166 for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) {
lib/Target/X86/X86ISelLowering.cpp 413 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
416 setOperationAction(ISD::SELECT, VT, Custom);
422 setOperationAction(ISD::SELECT, VT, Custom);
427 setOperationAction(ISD::SELECT, MVT::x86mmx, Custom);
822 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
928 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
929 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
930 setOperationAction(ISD::SELECT, MVT::v4i32, Custom);
931 setOperationAction(ISD::SELECT, MVT::v8i16, Custom);
932 setOperationAction(ISD::SELECT, MVT::v16i8, Custom);
1152 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1153 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1154 setOperationAction(ISD::SELECT, MVT::v8i32, Custom);
1155 setOperationAction(ISD::SELECT, MVT::v16i16, Custom);
1156 setOperationAction(ISD::SELECT, MVT::v32i8, Custom);
1157 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1298 setOperationAction(ISD::SELECT, MVT::v1i1, Custom);
1334 setOperationAction(ISD::SELECT, VT, Custom);
1429 setOperationAction(ISD::SELECT, VT, Custom);
1462 setOperationAction(ISD::SELECT, VT, Custom);
1608 setOperationAction(ISD::SELECT, VT, Custom);
1687 setOperationAction(ISD::SELECT, VT, Custom);
1845 setTargetDAGCombine(ISD::SELECT);
18266 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2);
18267 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3);
18269 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2);
18270 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3);
20010 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
20342 SDValue CMov = DAG.getNode(ISD::SELECT, DL, VT, Cmp, Add, N0);
27719 case ISD::SELECT: return LowerSELECT(Op, DAG);
36217 return DAG.getNode(ISD::SELECT, DL, VT, Ext0, Ext1, Ext2);
36989 if (Subtarget.hasAVX512() && N->getOpcode() == ISD::SELECT &&
36999 return DAG.getNode(ISD::SELECT, DL, VT, AndNode, RHS, LHS);
37072 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
37234 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::i64, Cond, LHS, RHS);
38680 case ISD::SELECT:
44909 case ISD::SELECT:
lib/Target/X86/X86TargetTransformInfo.cpp 1754 { ISD::SELECT, MVT::v32i16, 1 },
1755 { ISD::SELECT, MVT::v64i8, 1 },
1764 { ISD::SELECT, MVT::v8i64, 1 },
1765 { ISD::SELECT, MVT::v16i32, 1 },
1766 { ISD::SELECT, MVT::v8f64, 1 },
1767 { ISD::SELECT, MVT::v16f32, 1 },
1776 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb
1777 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb
1778 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb
1779 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb
1791 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd
1792 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps
1793 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd
1794 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps
1795 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps
1796 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps
1806 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd
1807 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps
1808 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb
1809 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb
1810 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb
1811 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb
1822 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd
1823 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por
1824 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por
1825 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por
1826 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por
1833 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps