reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/X86/X86GenDAGISel.inc

254409   return (N->getOperand(0).getOpcode() == ISD::SDIVREM &&

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 3513   unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
19604       Opcode != ISD::UDIVREM && Opcode != ISD::SDIVREM) {

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 2185   bool isSigned = Opcode == ISD::SDIVREM;
 3201     unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
 3220     unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
 4075   case ISD::SDIVREM:

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 3131   if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
 3132     SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
 3322   if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
 3323     SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

  368   case ISD::SDIVREM:

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  234   case ISD::SDIVREM:                    return "sdivrem";

lib/Target/AArch64/AArch64ISelLowering.cpp

  322   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
  323   setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
  325     setOperationAction(ISD::SDIVREM, VT, Expand);

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  314     setOperationAction(ISD::SDIVREM, VT, Custom);
  384     setOperationAction(ISD::SDIVREM, VT, Custom);
 1137   case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
 1981     SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),

lib/Target/AMDGPU/R600ISelLowering.cpp

  677   case ISD::SDIVREM: {

lib/Target/ARM/ARMISelLowering.cpp

 1164     setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
 1166     setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
 1169     setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
 9229   case ISD::SDIVREM:
 9297   case ISD::SDIVREM:
15918   assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
15921   bool isSigned = N->getOpcode() == ISD::SDIVREM ||
15936   assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
15939   bool isSigned = N->getOpcode() == ISD::SDIVREM ||
15963   assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
15965   bool isSigned = (Opcode == ISD::SDIVREM);

lib/Target/ARM/ARMTargetTransformInfo.cpp

  919       case ISD::SDIVREM:

lib/Target/AVR/AVRISelLowering.cpp

  156     setOperationAction(ISD::SDIVREM, VT, Custom);
  341   assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
  343   bool IsSigned = (Opcode == ISD::SDIVREM);
  705   case ISD::SDIVREM:

lib/Target/BPF/BPFISelLowering.cpp

   86     setOperationAction(ISD::SDIVREM, VT, Expand);

lib/Target/Hexagon/HexagonISelLowering.cpp

 1375         ISD::SDIVREM,   ISD::UDIVREM,   ISD::ROTL,      ISD::ROTR,
 1421     ISD::SREM,    ISD::UREM,    ISD::SDIVREM, ISD::UDIVREM,   ISD::SADDO,

lib/Target/Lanai/LanaiISelLowering.cpp

  108   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);

lib/Target/MSP430/MSP430ISelLowering.cpp

  132   setOperationAction(ISD::SDIVREM,          MVT::i8,    Promote);
  138   setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);

lib/Target/Mips/MipsISelLowering.cpp

  500   setTargetDAGCombine(ISD::SDIVREM);
  576   unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
 1160   case ISD::SDIVREM:

lib/Target/Mips/MipsSEISelLowering.cpp

  197     setOperationAction(ISD::SDIVREM,          MVT::i64, Custom);
  204   setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
  237     setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
  284     setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
  458   case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);

lib/Target/PowerPC/PPCISelLowering.cpp

  267   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
  269   setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
  654       setOperationAction(ISD::SDIVREM, VT, Expand);

lib/Target/RISCV/RISCVISelLowering.cpp

  127   setOperationAction(ISD::SDIVREM, XLenVT, Expand);

lib/Target/Sparc/SparcISelLowering.cpp

 1497   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
 1504     setOperationAction(ISD::SDIVREM, MVT::i64, Expand);

lib/Target/SystemZ/SystemZISelLowering.cpp

  163       setOperationAction(ISD::SDIVREM, VT, Custom);
 4962   case ISD::SDIVREM:

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  113         ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS,

lib/Target/X86/X86ISelDAGToDAG.cpp

 4794   case ISD::SDIVREM:
 4800     bool isSigned = Opcode == ISD::SDIVREM;

lib/Target/X86/X86ISelLowering.cpp

  765     setOperationAction(ISD::SDIVREM, VT, Expand);
 1820     setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
25397   case ISD::SDIVREM:   isSigned = true;  LC = RTLIB::SDIVREM_I128; break;
27964   case ISD::SDIVREM:

lib/Target/X86/X86TargetTransformInfo.cpp

 3399   return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);