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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc106604 /*238104*/ /*SwitchOpcode*/ 77|128,12/*1613*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->239721
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc78424 /*174355*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->174429
gen/lib/Target/ARM/ARMGenDAGISel.inc53550 /*119802*/ /*SwitchOpcode*/ 10|128,4/*522*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->120328
gen/lib/Target/PowerPC/PPCGenDAGISel.inc40903 /*102832*/ /*SwitchOpcode*/ 37|128,20/*2597*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->105433
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1711 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc25918 /* 49310*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
25956 /* 49373*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
26019 /* 49483*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
28338 /* 53645*/ /*SwitchOpcode*/ 59|128,1/*187*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->53836
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc20968 /* 40088*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->40162
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 976 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc35297 /* 73463*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
35620 /* 74182*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
41770 /* 87306*/ /*SwitchOpcode*/ 78|128,6/*846*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->88156
59154 /*124745*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
111759 /*231777*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->231852
111931 /*232113*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->232188
112103 /*232449*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->232524
112275 /*232785*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->232860
178782 /*362230*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->362305
178893 /*362445*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->362520
189160 /*382061*/ OPC_SwitchOpcode /*2 cases */, 120|128,7/*1016*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->383082
190219 /*384171*/ OPC_SwitchOpcode /*2 cases */, 120|128,7/*1016*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->385192
191278 /*386280*/ OPC_SwitchOpcode /*2 cases */, 40, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->386324
191774 /*387285*/ OPC_SwitchOpcode /*2 cases */, 40, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->387329
192160 /*388082*/ OPC_SwitchOpcode /*2 cases */, 40, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->388126
192704 /*389213*/ OPC_SwitchOpcode /*2 cases */, 40, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->389257
194116 /*392330*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
211542 /*428974*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
211582 /*429057*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->429137
232100 /*473309*/ OPC_SwitchOpcode /*2 cases */, 8|128,72/*9224*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->482538
233749 /*476667*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
234185 /*477581*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
236621 /*482695*/ OPC_SwitchOpcode /*2 cases */, 27|128,31/*3995*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->486695
238532 /*486839*/ OPC_SwitchOpcode /*3 cases */, 82|128,72/*9298*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->496142
240181 /*490197*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
240617 /*491111*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
243138 /*496403*/ /*SwitchOpcode*/ 29|128,31/*3997*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->500404
245015 /*500488*/ OPC_SwitchOpcode /*2 cases */, 79, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->500571
245173 /*500796*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
245245 /*500943*/ OPC_SwitchOpcode /*2 cases */, 61, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->501008
245412 /*501269*/ OPC_SwitchOpcode /*2 cases */, 40, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->501313
245537 /*501518*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
246637 /*503770*/ OPC_SwitchOpcode /*3 cases */, 56, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->503830
gen/lib/Target/X86/X86GenFastISel.inc 5921 case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0, Op0IsKill);
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1596 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
4344 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) &&
16814 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) {
16862 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) {
17000 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
17872 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR &&
17906 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), NVT, Scalar);
18532 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) {
18913 SDValue Insert = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, NewBO);
19212 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Val);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 406 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
1826 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1934 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1989 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1992 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2946 case ISD::SCALAR_TO_VECTOR:
4529 case ISD::SCALAR_TO_VECTOR: {
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 101 case ISD::SCALAR_TO_VECTOR:
1168 case ISD::SCALAR_TO_VECTOR:
3607 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
4160 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 58 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
282 ISD::SCALAR_TO_VECTOR, DL, OtherVT, SDValue(ScalarNode, OtherNo));
685 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
702 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
763 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res);
793 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
807 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
857 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
1531 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
2715 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
3562 NewVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewInVT, InOp);
3797 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
4741 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
4796 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2605 case ISD::SCALAR_TO_VECTOR: {
4632 case ISD::SCALAR_TO_VECTOR:
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 281 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 810 case ISD::SCALAR_TO_VECTOR: {
2120 case ISD::SCALAR_TO_VECTOR: {
lib/Target/AArch64/AArch64ISelLowering.cpp 6946 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
7625 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
7803 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op0);
11640 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
11642 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 418 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo);
698 assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
770 case ISD::SCALAR_TO_VECTOR:
2777 case ISD::SCALAR_TO_VECTOR:
lib/Target/AMDGPU/SIISelLowering.cpp 262 case ISD::SCALAR_TO_VECTOR:
291 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
292 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
520 case ISD::SCALAR_TO_VECTOR:
722 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
5466 AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VectorVT,
10037 case ISD::SCALAR_TO_VECTOR: {
lib/Target/ARM/ARMISelLowering.cpp 315 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
396 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
5466 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5468 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
7191 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
7825 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
lib/Target/Hexagon/HexagonISelLowering.cpp 1436 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 4950 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
lib/Target/PowerPC/PPCISelLowering.cpp 655 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
733 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
734 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
748 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
751 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
755 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
756 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
757 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
758 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
953 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
1001 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
1042 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
2534 UI->getOpcode() != ISD::SCALAR_TO_VECTOR)
8248 if (InputLoad->getOpcode() == ISD::SCALAR_TO_VECTOR)
10158 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
lib/Target/SystemZ/SystemZISelLowering.cpp 356 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
461 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
462 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
4478 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
4741 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
4765 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4910 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
5022 case ISD::SCALAR_TO_VECTOR:
lib/Target/X86/X86FastISel.cpp 2652 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR,
lib/Target/X86/X86ISelDAGToDAG.cpp 909 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT,
911 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT,
2345 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR && N.getNode()->hasOneUse()) {
lib/Target/X86/X86ISelLowering.cpp 908 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1269 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1504 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i16, Custom);
1651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v64i8, Custom);
1838 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
2558 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2790 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
3111 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
3783 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
6185 Op.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6785 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7039 case ISD::SCALAR_TO_VECTOR: {
7399 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7439 V = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, V);
7503 V = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Elt);
7756 case ISD::SCALAR_TO_VECTOR:
9693 SDValue S2V = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, VarElt);
9708 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
9715 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
9725 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShufVT, Item);
9737 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
9751 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
9833 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
9864 Ops[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
9906 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
9924 Ops[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
12238 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
12299 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
12391 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
12583 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0))) {
12637 V = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
12970 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
17539 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i1, Elt);
17591 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
17618 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
17662 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
17667 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
17698 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
17712 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
18348 SDValue InVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecInVT, Src);
18576 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
18614 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
18628 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
18630 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
19794 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
19843 Sign = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Sign);
19857 Mag = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Mag);
19878 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, N0);
21250 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
21251 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
21252 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
21270 SDValue Cmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i1, Cond);
22543 ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v2i64, ShAmt);
22550 ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), AmtTy, ShAmt);
22565 ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v4i32, ShAmt);
26819 Src = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Src);
27009 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, In);
27222 SDValue SclToVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
27682 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, Subtarget,DAG);
27836 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, N->getOperand(0));
28530 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Res);
32442 V1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
33501 if (Src.getOpcode() == ISD::SCALAR_TO_VECTOR)
33604 SDValue SclVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Scl);
33707 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT,
35399 V = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v4f32, V);
38730 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
40514 StoredVal.getOpcode() == ISD::SCALAR_TO_VECTOR &&
42369 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, BroadcastVT, N00);
42379 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Scl);
44315 if (Op0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
44761 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i1,
44779 VT, DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v4i32,
44896 case ISD::SCALAR_TO_VECTOR: