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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc99096 /*223331*/ /*SwitchOpcode*/ 30|128,1/*158*/, TARGET_VAL(ISD::MULHU),// ->223493
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7733 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc63563 /*138780*/ /*SwitchOpcode*/ 12, TARGET_VAL(ISD::MULHU),// ->138795
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 8134 /* 31091*/ /*SwitchOpcode*/ 53|128,2/*309*/, TARGET_VAL(ISD::MULHU),// ->31404
gen/lib/Target/ARC/ARCGenDAGISel.inc 871 /* 1467*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::MULHU),// ->1518
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc67757 /*130773*/ /*SwitchOpcode*/ 39|128,5/*679*/, TARGET_VAL(ISD::MULHU),// ->131456
gen/lib/Target/Mips/MipsGenDAGISel.inc25873 /* 49015*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::MULHU),// ->49060
gen/lib/Target/Mips/MipsGenFastISel.inc 3416 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc57995 /*123288*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::MULHU),// ->123372
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28524 /* 68543*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::MULHU),// ->68570
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3245 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc12179 /* 22666*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::MULHU),// ->22711
gen/lib/Target/X86/X86GenDAGISel.inc78198 /*164477*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::MULHU),// ->164562
83302 /*174564*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::MULHU),// ->174647
100905 /*209660*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::MULHU),// ->209745
108305 /*224511*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::MULHU),// ->224594
120962 /*249632*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::MULHU),// ->249796
124283 /*255994*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::MULHU),// ->256016
126728 /*260585*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::MULHU),// ->260606
145448 /*297651*/ OPC_CheckOpcode, TARGET_VAL(ISD::MULHU),
147398 /*301245*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::MULHU),// ->301266
187149 /*378284*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::MULHU),// ->378306
187938 /*379749*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::MULHU),// ->379770
213854 /*433971*/ /*SwitchOpcode*/ 126|128,2/*382*/, TARGET_VAL(ISD::MULHU),// ->434357
gen/lib/Target/X86/X86GenFastISel.inc13519 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/TargetLowering.h 2267 case ISD::MULHU:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1518 case ISD::MULHU: return visitMULHU(N);
4134 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3230 case ISD::MULHU:
3233 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
3248 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3286 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 363 case ISD::MULHU:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 933 case ISD::MULHU:
2736 case ISD::MULHU:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 5102 case ISD::MULHU:
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 226 case ISD::MULHU: return "mulhu";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 4829 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT)
4830 : isOperationLegalOrCustom(ISD::MULHU, VT))
4831 return DAG.getNode(ISD::MULHU, dl, VT, X, Y);
5598 isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
5626 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
7022 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU;
7206 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
lib/Target/AArch64/AArch64FastISel.cpp 3803 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
lib/Target/AArch64/AArch64ISelLowering.cpp 761 setOperationAction(ISD::MULHU, VT, Legal);
764 setOperationAction(ISD::MULHU, VT, Expand);
2195 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 526 if (TLI->isOperationLegalOrCustom(ISD::MULHU, VT)) {
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 338 setOperationAction(ISD::MULHU, MVT::i64, Expand);
367 setOperationAction(ISD::MULHU, VT, Expand);
495 setTargetDAGCombine(ISD::MULHU);
1700 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
1715 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
1729 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
1869 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1881 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1894 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
3963 case ISD::MULHU:
lib/Target/ARC/ARCISelLowering.cpp 112 setOperationAction(ISD::MULHU, MVT::i32, Legal);
lib/Target/ARM/ARMISelLowering.cpp 719 setOperationAction(ISD::MULHU, VT, Expand);
1037 setOperationAction(ISD::MULHU, MVT::i32, Expand);
lib/Target/AVR/AVRISelLowering.cpp 176 setOperationAction(ISD::MULHU, VT, Expand);
lib/Target/BPF/BPFISelLowering.cpp 90 setOperationAction(ISD::MULHU, VT, Expand);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 93 setOperationAction(ISD::MULHU, T, Custom);
152 setOperationAction(ISD::MULHU, T, Custom);
1537 case ISD::MULHU:
1572 case ISD::MULHU: return LowerHvxMulh(Op, DAG);
lib/Target/Lanai/LanaiISelLowering.cpp 114 setOperationAction(ISD::MULHU, MVT::i32, Expand);
lib/Target/MSP430/MSP430ISelLowering.cpp 119 setOperationAction(ISD::MULHU, MVT::i8, Promote);
124 setOperationAction(ISD::MULHU, MVT::i16, Expand);
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 211 case ISD::MULHU: {
212 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
lib/Target/Mips/MipsSEISelLowering.cpp 185 setOperationAction(ISD::MULHU, MVT::i32, Custom);
196 setOperationAction(ISD::MULHU, MVT::i64, Custom);
233 setOperationAction(ISD::MULHU, MVT::i32, Legal);
280 setOperationAction(ISD::MULHU, MVT::i64, Legal);
456 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
lib/Target/PowerPC/PPCISelLowering.cpp 649 setOperationAction(ISD::MULHU, VT, Expand);
lib/Target/RISCV/RISCVISelLowering.cpp 113 setOperationAction(ISD::MULHU, XLenVT, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1648 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1671 setOperationAction(ISD::MULHU, MVT::i64, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 199 setOperationAction(ISD::MULHU, VT, Expand);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 112 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
lib/Target/X86/X86ISelLowering.cpp 311 setOperationAction(ISD::MULHU, VT, Expand);
764 setOperationAction(ISD::MULHU, VT, Expand);
861 setOperationAction(ISD::MULHU, MVT::v4i32, Custom);
863 setOperationAction(ISD::MULHU, MVT::v16i8, Custom);
865 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
1197 setOperationAction(ISD::MULHU, MVT::v8i32, Custom);
1199 setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1201 setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
1446 setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
1641 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1643 setOperationAction(ISD::MULHU, MVT::v64i8, Custom);
25892 SDValue Res = DAG.getNode(ISD::MULHU, dl, VT, R, Scale);
26406 SDValue Hi = DAG.getNode(ISD::MULHU, DL, VT, R, Scale);
27748 case ISD::MULHU: return LowerMULH(Op, Subtarget, DAG);
37905 SDValue MulHi = DAG.getNode(Mode == MULS16 ? ISD::MULHS : ISD::MULHU, DL,
41211 unsigned Opc = ExtOpc == ISD::SIGN_EXTEND ? ISD::MULHS : ISD::MULHU;
lib/Target/X86/X86IntrinsicsInfo.h 388 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
843 X86_INTRINSIC_DATA(avx512_pmulhu_w_512, INTR_TYPE_2OP, ISD::MULHU, 0),
1053 X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
lib/Target/XCore/XCoreISelLowering.cpp 100 setOperationAction(ISD::MULHU, MVT::i32, Expand);