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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc99042 /*223169*/ /*SwitchOpcode*/ 30|128,1/*158*/, TARGET_VAL(ISD::MULHS),// ->223331
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7732 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc63571 /*138795*/ /*SwitchOpcode*/ 12, TARGET_VAL(ISD::MULHS),// ->138810
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 8057 /* 30778*/ /*SwitchOpcode*/ 53|128,2/*309*/, TARGET_VAL(ISD::MULHS),// ->31091
gen/lib/Target/ARC/ARCGenDAGISel.inc 842 /* 1416*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::MULHS),// ->1467
gen/lib/Target/ARM/ARMGenDAGISel.inc 5372 /* 10955*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::MULHS),// ->10983
5457 /* 11135*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::MULHS),// ->11163
5595 /* 11429*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::MULHS),// ->11456
5652 /* 11548*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::MULHS),// ->11575
38027 /* 83743*/ /*SwitchOpcode*/ 44, TARGET_VAL(ISD::MULHS),// ->83790
gen/lib/Target/ARM/ARMGenFastISel.inc 5172 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc67514 /*129901*/ /*SwitchOpcode*/ 100|128,6/*868*/, TARGET_VAL(ISD::MULHS),// ->130773
gen/lib/Target/Mips/MipsGenDAGISel.inc25849 /* 48970*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::MULHS),// ->49015
gen/lib/Target/Mips/MipsGenFastISel.inc 3415 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc57950 /*123204*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::MULHS),// ->123288
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28510 /* 68516*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::MULHS),// ->68543
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3244 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc12155 /* 22621*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::MULHS),// ->22666
gen/lib/Target/X86/X86GenDAGISel.inc78150 /*164392*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::MULHS),// ->164477
83258 /*174481*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::MULHS),// ->174564
100857 /*209575*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::MULHS),// ->209660
108261 /*224428*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::MULHS),// ->224511
120872 /*249468*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::MULHS),// ->249632
124270 /*255972*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::MULHS),// ->255994
126717 /*260564*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::MULHS),// ->260585
145434 /*297628*/ OPC_CheckOpcode, TARGET_VAL(ISD::MULHS),
147387 /*301224*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::MULHS),// ->301245
187136 /*378262*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::MULHS),// ->378284
187927 /*379728*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::MULHS),// ->379749
214040 /*434357*/ /*SwitchOpcode*/ 126|128,2/*382*/, TARGET_VAL(ISD::MULHS),// ->434743
gen/lib/Target/X86/X86GenFastISel.inc13518 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/TargetLowering.h 2268 case ISD::MULHS:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1519 case ISD::MULHS: return visitMULHS(N);
4103 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3231 case ISD::MULHS: {
3248 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3285 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 362 case ISD::MULHS:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 932 case ISD::MULHS:
2735 case ISD::MULHS:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 5103 case ISD::MULHS:
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 227 case ISD::MULHS: return "mulhs";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 4709 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT)
4710 : isOperationLegalOrCustom(ISD::MULHS, VT))
4711 Q = DAG.getNode(ISD::MULHS, dl, VT, N0, MagicFactor);
5596 isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
5626 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
7022 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU;
7207 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
lib/Target/AArch64/AArch64FastISel.cpp 3771 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
lib/Target/AArch64/AArch64ISelLowering.cpp 760 setOperationAction(ISD::MULHS, VT, Legal);
763 setOperationAction(ISD::MULHS, VT, Expand);
2186 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 339 setOperationAction(ISD::MULHS, MVT::i64, Expand);
368 setOperationAction(ISD::MULHS, VT, Expand);
496 setTargetDAGCombine(ISD::MULHS);
3961 case ISD::MULHS:
lib/Target/ARC/ARCISelLowering.cpp 111 setOperationAction(ISD::MULHS, MVT::i32, Legal);
lib/Target/ARM/ARMISelLowering.cpp 717 setOperationAction(ISD::MULHS, VT, Expand);
1044 setOperationAction(ISD::MULHS, MVT::i32, Expand);
lib/Target/AVR/AVRISelLowering.cpp 175 setOperationAction(ISD::MULHS, VT, Expand);
lib/Target/BPF/BPFISelLowering.cpp 91 setOperationAction(ISD::MULHS, VT, Expand);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 92 setOperationAction(ISD::MULHS, T, Custom);
151 setOperationAction(ISD::MULHS, T, Custom);
1331 bool IsSigned = Op.getOpcode() == ISD::MULHS;
1536 case ISD::MULHS:
1571 case ISD::MULHS:
lib/Target/Lanai/LanaiISelLowering.cpp 115 setOperationAction(ISD::MULHS, MVT::i32, Expand);
lib/Target/MSP430/MSP430ISelLowering.cpp 118 setOperationAction(ISD::MULHS, MVT::i8, Promote);
123 setOperationAction(ISD::MULHS, MVT::i16, Expand);
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 210 case ISD::MULHS:
lib/Target/Mips/MipsSEISelLowering.cpp 184 setOperationAction(ISD::MULHS, MVT::i32, Custom);
195 setOperationAction(ISD::MULHS, MVT::i64, Custom);
232 setOperationAction(ISD::MULHS, MVT::i32, Legal);
279 setOperationAction(ISD::MULHS, MVT::i64, Legal);
455 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
lib/Target/PowerPC/PPCISelLowering.cpp 650 setOperationAction(ISD::MULHS, VT, Expand);
lib/Target/RISCV/RISCVISelLowering.cpp 112 setOperationAction(ISD::MULHS, XLenVT, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1649 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1672 setOperationAction(ISD::MULHS, MVT::i64, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 198 setOperationAction(ISD::MULHS, VT, Expand);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 112 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
lib/Target/X86/X86ISelLowering.cpp 310 setOperationAction(ISD::MULHS, VT, Expand);
762 setOperationAction(ISD::MULHS, VT, Expand);
862 setOperationAction(ISD::MULHS, MVT::v4i32, Custom);
864 setOperationAction(ISD::MULHS, MVT::v16i8, Custom);
866 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
1198 setOperationAction(ISD::MULHS, MVT::v8i32, Custom);
1200 setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom);
1202 setOperationAction(ISD::MULHS, MVT::v32i8, Custom);
1447 setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
1640 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1642 setOperationAction(ISD::MULHS, MVT::v64i8, Custom);
25167 bool IsSigned = Op->getOpcode() == ISD::MULHS;
25915 SDValue Res = DAG.getNode(ISD::MULHS, dl, VT, R, Scale);
27747 case ISD::MULHS:
37905 SDValue MulHi = DAG.getNode(Mode == MULS16 ? ISD::MULHS : ISD::MULHU, DL,
41211 unsigned Opc = ExtOpc == ISD::SIGN_EXTEND ? ISD::MULHS : ISD::MULHU;
lib/Target/X86/X86IntrinsicsInfo.h 387 X86_INTRINSIC_DATA(avx2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
842 X86_INTRINSIC_DATA(avx512_pmulh_w_512, INTR_TYPE_2OP, ISD::MULHS, 0),
1052 X86_INTRINSIC_DATA(sse2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
lib/Target/XCore/XCoreISelLowering.cpp 99 setOperationAction(ISD::MULHS, MVT::i32, Expand);