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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc109500 /*244653*/ /*SwitchOpcode*/ 100|128,12/*1636*/, TARGET_VAL(ISD::INSERT_VECTOR_ELT),// ->246293
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc77319 /*171903*/ /*SwitchOpcode*/ 72|128,18/*2376*/, TARGET_VAL(ISD::INSERT_VECTOR_ELT),// ->174283
gen/lib/Target/AMDGPU/R600GenDAGISel.inc10833 /* 41463*/ /*SwitchOpcode*/ 36|128,2/*292*/, TARGET_VAL(ISD::INSERT_VECTOR_ELT),// ->41759
gen/lib/Target/ARM/ARMGenDAGISel.inc45791 /*101490*/ /*SwitchOpcode*/ 23|128,8/*1047*/, TARGET_VAL(ISD::INSERT_VECTOR_ELT),// ->102541
gen/lib/Target/Mips/MipsGenDAGISel.inc28742 /* 54359*/ /*SwitchOpcode*/ 90|128,2/*346*/, TARGET_VAL(ISD::INSERT_VECTOR_ELT),// ->54709
gen/lib/Target/PowerPC/PPCGenDAGISel.inc42115 /*105723*/ /*SwitchOpcode*/ 12|128,5/*652*/, TARGET_VAL(ISD::INSERT_VECTOR_ELT),// ->106379
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc26190 /* 49777*/ /*SwitchOpcode*/ 66|128,8/*1090*/, TARGET_VAL(ISD::INSERT_VECTOR_ELT),// ->50871
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc20810 /* 39784*/ /*SwitchOpcode*/ 23|128,2/*279*/, TARGET_VAL(ISD::INSERT_VECTOR_ELT),// ->40067
gen/lib/Target/X86/X86GenDAGISel.inc197873 /*400372*/ /*SwitchOpcode*/ 45|128,2/*301*/, TARGET_VAL(ISD::INSERT_VECTOR_ELT),// ->400677
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1590 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
16628 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
16633 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT,
16636 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
16807 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT &&
18793 if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT)
18812 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Shuf), Op0.getValueType(),
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2949 case ISD::INSERT_VECTOR_ELT:
4129 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4479 case ISD::INSERT_VECTOR_ELT: {
4522 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 97 case ISD::INSERT_VECTOR_ELT:
1166 case ISD::INSERT_VECTOR_ELT:
3606 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
4263 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp 432 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx);
436 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx);
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 56 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
856 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
1459 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
1463 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
2713 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2977 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
3704 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
4633 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem,
4754 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3175 case ISD::INSERT_VECTOR_ELT: {
3759 case ISD::INSERT_VECTOR_ELT: {
5270 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
5506 case ISD::INSERT_VECTOR_ELT: {
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3524 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 276 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 703 case ISD::INSERT_VECTOR_ELT: {
836 case ISD::INSERT_VECTOR_ELT: {
2310 case ISD::INSERT_VECTOR_ELT: {
lib/CodeGen/TargetLoweringBase.cpp 1639 case InsertElement: return ISD::INSERT_VECTOR_ELT;
lib/Target/AArch64/AArch64ISelLowering.cpp 617 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
3028 case ISD::INSERT_VECTOR_ELT:
7046 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
7757 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
7813 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
7826 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
7851 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
10768 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
11774 case ISD::INSERT_VECTOR_ELT:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1445 : ISD::INSERT_VECTOR_ELT,
lib/Target/AMDGPU/R600ISelLowering.cpp 210 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
211 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
212 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
213 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
279 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
479 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
735 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
1898 case ISD::INSERT_VECTOR_ELT: {
lib/Target/AMDGPU/SIISelLowering.cpp 259 case ISD::INSERT_VECTOR_ELT:
288 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
289 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
305 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom);
306 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);
307 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
308 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
316 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom);
317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
318 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom);
322 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
323 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
517 case ISD::INSERT_VECTOR_ELT:
726 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
4044 case ISD::INSERT_VECTOR_ELT:
4253 case ISD::INSERT_VECTOR_ELT: {
4779 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt,
4815 SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16,
8824 case ISD::INSERT_VECTOR_ELT: {
10057 case ISD::INSERT_VECTOR_ELT:
lib/Target/ARM/ARMISelLowering.cpp 163 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
250 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
310 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
311 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
355 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
393 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
924 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
1967 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1981 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
4042 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
4045 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
7084 Base = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Base, V,
7217 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
7236 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
7321 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
8050 SDValue IVecOut = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, IVecVT,
8134 ConVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ConcatVT, ConVec, Elt,
8164 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
8168 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
8201 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt,
9196 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
12763 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
12810 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
14439 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
lib/Target/Hexagon/HexagonISelLowering.cpp 1437 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1481 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
2846 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 98 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom);
189 setOperationAction(ISD::INSERT_VECTOR_ELT, BoolV, Custom);
1559 case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG);
lib/Target/Mips/MipsSEISelLowering.cpp 328 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
382 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
1962 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
2525 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
lib/Target/NVPTX/NVPTXISelLowering.cpp 389 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Expand);
lib/Target/PowerPC/PPCISelLowering.cpp 647 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
871 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
872 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
925 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
949 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
997 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
1038 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
9624 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT &&
10160 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
lib/Target/PowerPC/PPCTargetTransformInfo.cpp 789 if (ISD == ISD::INSERT_VECTOR_ELT)
822 if (ISD == ISD::INSERT_VECTOR_ELT)
830 ISD == ISD::INSERT_VECTOR_ELT)
lib/Target/Sparc/SparcISelLowering.cpp 995 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
1001 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 1572 case ISD::INSERT_VECTOR_ELT: {
lib/Target/SystemZ/SystemZISelLowering.cpp 340 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
466 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
467 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
4717 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
4789 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL,
4819 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT,
5024 case ISD::INSERT_VECTOR_ELT:
5887 if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT && Op.hasOneUse()) {
5912 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VecVT,
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 154 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) {
1002 case ISD::INSERT_VECTOR_ELT:
1441 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane,
lib/Target/X86/X86ISelLowering.cpp 752 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
892 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
923 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1267 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1345 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1500 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1607 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1657 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1658 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
7444 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V, Op.getOperand(i),
7509 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, Elt,
8414 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
8475 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
8567 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
9644 (isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT) ||
9683 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ld, VarElt, InsIndex);
9912 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
17532 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
17606 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
27679 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
28194 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecInVT,
36296 Rdx = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, MVT::v4i32,
40349 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT,
41445 if (Opc == ISD::INSERT_VECTOR_ELT) {
41454 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), VT, InsVector,