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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc 2140 /* 3954*/ /*SwitchOpcode*/ 102|128,4/*614*/, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->4572
72961 /*173902*/ OPC_SwitchOpcode /*2 cases */, 95, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->174001
73621 /*175147*/ OPC_SwitchOpcode /*2 cases */, 95, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->175246
85099 /*196959*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
86224 /*199155*/ OPC_SwitchOpcode /*4 cases */, 85|128,2/*341*/, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->199501
101998 /*228410*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
102034 /*228482*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
102713 /*229766*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
102760 /*229869*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
110806 /*247500*/ /*SwitchOpcode*/ 46|128,2/*302*/, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->247806
gen/lib/Target/ARM/ARMGenDAGISel.inc49275 /*109665*/ /*SwitchOpcode*/ 16|128,1/*144*/, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->109813
gen/lib/Target/X86/X86GenDAGISel.inc 7465 /* 16014*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
7479 /* 16041*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
7554 /* 16212*/ OPC_SwitchOpcode /*2 cases */, 85, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->16301
75550 /*159357*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
75900 /*160034*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
76384 /*160956*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
80728 /*169325*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
81180 /*170257*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
85667 /*179415*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
85793 /*179660*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
86532 /*181097*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
91395 /*190471*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
92233 /*192199*/ /*SwitchOpcode*/ 83, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->192285
97529 /*203099*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
97845 /*203720*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
98662 /*205310*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
104648 /*216977*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
105434 /*218639*/ /*SwitchOpcode*/ 34|128,2/*290*/, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->218933
122947 /*253607*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
123374 /*254341*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
125655 /*258421*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
128017 /*263178*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
128154 /*263435*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
129460 /*265955*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
133811 /*274446*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
135003 /*276962*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->277069
140344 /*288141*/ /*SwitchOpcode*/ 95, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->288239
140844 /*288992*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
142363 /*291706*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
144405 /*295798*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
144628 /*296179*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
146545 /*299531*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
148387 /*303231*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
148501 /*303442*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
149240 /*304849*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
151918 /*309790*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
152597 /*311193*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
155800 /*317483*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
156070 /*317942*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
157139 /*319767*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
158456 /*322299*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
158956 /*323174*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
160451 /*325836*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
162141 /*329232*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
162174 /*329293*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
163402 /*331660*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
167453 /*339578*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
168599 /*341984*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->342020
173751 /*352790*/ /*SwitchOpcode*/ 30, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->352823
174238 /*353622*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
175249 /*355462*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
193762 /*391495*/ /*SwitchOpcode*/ 62|128,39/*5054*/, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->396553
229108 /*467578*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
229138 /*467629*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
229194 /*467767*/ /*SwitchOpcode*/ 51|128,1/*179*/, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->467950
229220 /*467812*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
229291 /*467978*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
229346 /*468098*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
229408 /*468246*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1597 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
17225 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1,
18020 if (V.getOpcode() == ISD::INSERT_SUBVECTOR &&
18326 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) {
19284 SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N),
19293 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR &&
19296 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0.getOperand(0),
19302 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR &&
19304 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0,
19341 if (NewIdx && hasOperation(ISD::INSERT_SUBVECTOR, NewVT)) {
19343 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, NewVT, Res, N1Src, NewIdx);
19353 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() &&
19359 SDValue NewOp = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT,
19362 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N0.getNode()),
19622 if (LHS.getOpcode() == ISD::INSERT_SUBVECTOR && LHS.getOperand(0).isUndef() &&
19623 RHS.getOpcode() == ISD::INSERT_SUBVECTOR && RHS.getOperand(0).isUndef() &&
19637 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, VecC, NarrowBO, Z);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2940 case ISD::INSERT_SUBVECTOR:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 981 ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), Src,
1041 ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), Src,
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 853 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
1187 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
3230 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT),
3233 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT),
4241 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2556 case ISD::INSERT_SUBVECTOR: {
3852 case ISD::INSERT_SUBVECTOR: {
5354 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) &&
5522 case ISD::INSERT_SUBVECTOR: {
9329 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 279 case ISD::INSERT_SUBVECTOR: return "insert_subvector";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 874 case ISD::INSERT_SUBVECTOR: {
2259 case ISD::INSERT_SUBVECTOR: {
2281 TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 509 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
lib/Target/AArch64/AArch64ISelLowering.cpp 6228 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1442 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad,
1444 Join = DAG.getNode(HiVT.isVector() ? ISD::INSERT_SUBVECTOR
lib/Target/AMDGPU/SIISelLowering.cpp 260 case ISD::INSERT_SUBVECTOR:
326 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom);
327 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom);
328 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom);
329 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom);
332 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom);
333 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom);
334 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i32, Custom);
335 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8f32, Custom);
518 case ISD::INSERT_SUBVECTOR:
4042 case ISD::INSERT_SUBVECTOR:
lib/Target/Hexagon/HexagonISelLowering.cpp 1438 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1483 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
2845 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 97 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom);
188 setOperationAction(ISD::INSERT_SUBVECTOR, BoolV, Custom);
1558 case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG);
lib/Target/X86/X86ISelDAGToDAG.cpp 706 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR &&
lib/Target/X86/X86ISelLowering.cpp 754 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
1270 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1344 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1505 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1615 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1616 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1646 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Legal);
1647 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Legal);
1841 setTargetDAGCombine(ISD::INSERT_SUBVECTOR);
5524 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
5549 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, Vec,
5578 if (N->getOpcode() == ISD::INSERT_SUBVECTOR &&
5589 Src.getOpcode() == ISD::INSERT_SUBVECTOR &&
5683 Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5701 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec,
5706 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5713 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5744 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5749 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
5765 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx);
6199 if (Op.getOpcode() == ISD::INSERT_SUBVECTOR &&
6975 case ISD::INSERT_SUBVECTOR: {
7023 Ops.push_back(DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), AltVT,
7190 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), SrcVT,
7222 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), SrcVT,
7368 if (Opcode == ISD::INSERT_SUBVECTOR &&
7970 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT),
9997 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec,
10045 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ShiftVT,
10062 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, SubVec,
10081 SDValue Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT,
10084 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Op.getOperand(1),
12540 case ISD::INSERT_SUBVECTOR: {
14832 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
14861 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec,
15167 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V,
15196 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,
15206 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,
15565 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v32i8,
16277 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
16292 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec,
16800 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT,
16884 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
16903 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT,
17358 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVecVT,
17541 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VecVT, Vec, EltInVec,
17748 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVecVT,
19142 In = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT, DAG.getUNDEF(InVT),
19542 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8f64,
21545 In = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, InVT, DAG.getUNDEF(InVT),
21845 StoredVal = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1,
23096 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1,
23142 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1,
23202 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1,
27380 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NVT, FillVal,
27680 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
32343 if (Src.getOpcode() == ISD::INSERT_SUBVECTOR &&
34221 N->getOperand(0).getOpcode() == ISD::INSERT_SUBVECTOR &&
34227 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT,
37046 Cond = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcCondVT,
38711 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v16i1,
42747 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VecVT,
44428 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR &&
44431 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT,
44443 SubVec.getOperand(0).getOpcode() == ISD::INSERT_SUBVECTOR) {
44448 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT,
44493 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT,
44671 InVec.getOpcode() == ISD::INSERT_SUBVECTOR && IdxVal == 0 &&
44676 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
44904 case ISD::INSERT_SUBVECTOR: