reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

70966 /*149627*/  /*SwitchOpcode*/ 12, TARGET_VAL(ISD::FSIN),// ->149642

gen/lib/Target/X86/X86GenDAGISel.inc

75464 /*159185*/  /*SwitchOpcode*/ 37, TARGET_VAL(ISD::FSIN),// ->159225

gen/lib/Target/X86/X86GenFastISel.inc

 5919   case ISD::FSIN: return fastEmit_ISD_FSIN_r(VT, RetVT, Op0, Op0IsKill);

include/llvm/CodeGen/BasicTTIImpl.h

 1212       ISDs.push_back(ISD::FSIN);

include/llvm/CodeGen/TargetLowering.h

  950       case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 2262   unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
 2263     ? ISD::FCOS : ISD::FSIN;
 3113   case ISD::FSIN:
 3839   case ISD::FSIN:
 4394   case ISD::FSIN:

lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

   94     case ISD::FSIN:        R = SoftenFloatRes_FSIN(N); break;
 1164   case ISD::FSIN:       ExpandFloatRes_FSIN(N, Lo, Hi); break;
 2068     case ISD::FSIN:

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

  413   case ISD::FSIN:

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

   96   case ISD::FSIN:
  913   case ISD::FSIN:
 2865   case ISD::FSIN:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 4002   case ISD::FSIN:
 7763   case ISD::STRICT_FSIN:       NewOpc = ISD::FSIN;       break;

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 6038     case Intrinsic::sin:       Opcode = ISD::FSIN;       break;
 7598         if (visitUnaryFloatCall(I, ISD::FSIN))

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  194   case ISD::FSIN:                       return "fsin";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 5450   case ISD::FSIN:
 5566   case ISD::FSIN:

lib/Target/AArch64/AArch64ISelLowering.cpp

  248   setOperationAction(ISD::FSIN, MVT::f128, Expand);
  349   setOperationAction(ISD::FSIN, MVT::f32, Expand);
  350   setOperationAction(ISD::FSIN, MVT::f64, Expand);
  374   setOperationAction(ISD::FSIN,    MVT::f16,   Promote);
  375   setOperationAction(ISD::FSIN,    MVT::v4f16, Expand);
  376   setOperationAction(ISD::FSIN,    MVT::v8f16, Expand);
  677     setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
  828     setOperationAction(ISD::FSIN, VT, Expand);

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  424     setOperationAction(ISD::FSIN, VT, Expand);
  525   case ISD::FSIN:
 3777   case ISD::FSIN:

lib/Target/AMDGPU/R600ISelLowering.cpp

  141   setOperationAction(ISD::FSIN, MVT::f32, Custom);
  486   case ISD::FSIN: return LowerTrig(Op, DAG);
  773   case ISD::FSIN:

lib/Target/AMDGPU/SIISelLowering.cpp

  427   setOperationAction(ISD::FSIN, MVT::f32, Custom);
  491     setOperationAction(ISD::FSIN, MVT::f16, Promote);
 4026   case ISD::FSIN:
 7965   case ISD::FSIN:
 8579   case ISD::FSIN:
 8773   case ISD::FSIN:

lib/Target/ARM/ARMISelLowering.cpp

  336       setOperationAction(ISD::FSIN, VT, Expand);
  781     setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
  802     setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
  818     setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
  947     setOperationAction(ISD::FSIN,       MVT::f64, Expand);
 1298   setOperationAction(ISD::FSIN,      MVT::f64, Expand);
 1299   setOperationAction(ISD::FSIN,      MVT::f32, Expand);
 1374     setOperationAction(ISD::FSIN, MVT::f16, Promote);

lib/Target/Hexagon/HexagonISelLowering.cpp

 1383        {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
 1428     ISD::FREM,    ISD::FNEG,    ISD::FABS,    ISD::FSQRT,   ISD::FSIN,

lib/Target/Mips/MipsISelLowering.cpp

  436   setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
  437   setOperationAction(ISD::FSIN,              MVT::f64,   Expand);

lib/Target/Mips/MipsSEISelLowering.cpp

  148     setOperationAction(ISD::FSIN, MVT::f16, Promote);

lib/Target/NVPTX/NVPTXISelLowering.cpp

  571   for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,

lib/Target/PowerPC/PPCISelLowering.cpp

  272   setOperationAction(ISD::FSIN , MVT::f64, Expand);
  277   setOperationAction(ISD::FSIN , MVT::f32, Expand);
  638       setOperationAction(ISD::FSIN, VT, Expand);
  913         setOperationAction(ISD::FSIN , MVT::f128, Expand);
  964     setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
 1009     setOperationAction(ISD::FSIN , MVT::v4f32, Expand);

lib/Target/RISCV/RISCVISelLowering.cpp

  149       ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,

lib/Target/Sparc/SparcISelLowering.cpp

 1616   setOperationAction(ISD::FSIN , MVT::f128, Expand);
 1621   setOperationAction(ISD::FSIN , MVT::f64, Expand);
 1626   setOperationAction(ISD::FSIN , MVT::f32, Expand);

lib/Target/SystemZ/SystemZISelLowering.cpp

  432       setOperationAction(ISD::FSIN, VT, Expand);

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

   93          {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA})

lib/Target/X86/X86ISelLowering.cpp

  544       setOperationAction(ISD::FSIN   , VT, Expand);
  575     setOperationAction(ISD::FSIN   , MVT::f32, Expand);
  581       setOperationAction(ISD::FSIN, MVT::f64, Expand);
  596       setOperationAction(ISD::FSIN   , VT, Expand);
  648     setOperationAction(ISD::FSIN   , MVT::f80, Expand);
  681     setOperationAction(ISD::FSIN,    MVT::f128, Expand);
  730     setOperationAction(ISD::FSIN,      VT, Expand);
 1832           ISD::FLOG10, ISD::FPOW, ISD::FSIN})