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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc94226 /*214092*/ /*SwitchOpcode*/ 62|128,4/*574*/, TARGET_VAL(ISD::FP_TO_UINT),// ->214670
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4284 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc58164 /*127455*/ /*SwitchOpcode*/ 15|128,1/*143*/, TARGET_VAL(ISD::FP_TO_UINT),// ->127602
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 7871 /* 30041*/ /*SwitchOpcode*/ 78|128,1/*206*/, TARGET_VAL(ISD::FP_TO_UINT),// ->30251
gen/lib/Target/ARM/ARMGenDAGISel.inc22537 /* 48434*/ /*SwitchOpcode*/ 105, TARGET_VAL(ISD::FP_TO_UINT),// ->48542
37277 /* 82065*/ /*SwitchOpcode*/ 85|128,4/*597*/, TARGET_VAL(ISD::FP_TO_UINT),// ->82666
gen/lib/Target/ARM/ARMGenFastISel.inc 2719 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc67133 /*128947*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::FP_TO_UINT),// ->128999
gen/lib/Target/Mips/MipsGenDAGISel.inc29123 /* 55072*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::FP_TO_UINT),// ->55100
gen/lib/Target/Mips/MipsGenFastISel.inc 1205 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc69165 /*146095*/ /*SwitchOpcode*/ 2|128,2/*258*/, TARGET_VAL(ISD::FP_TO_UINT),// ->146357
gen/lib/Target/PowerPC/PPCGenDAGISel.inc19158 /* 48480*/ /*SwitchOpcode*/ 122, TARGET_VAL(ISD::FP_TO_UINT),// ->48605
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1707 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 5362 /* 9934*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_TO_UINT),
5488 /* 10142*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_TO_UINT),
12557 /* 23377*/ /*SwitchOpcode*/ 97|128,1/*225*/, TARGET_VAL(ISD::FP_TO_UINT),// ->23606
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc21971 /* 41239*/ /*SwitchOpcode*/ 52|128,1/*180*/, TARGET_VAL(ISD::FP_TO_UINT),// ->41423
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18517 /* 35467*/ /*SwitchOpcode*/ 5|128,1/*133*/, TARGET_VAL(ISD::FP_TO_UINT),// ->35604
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 972 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc41433 /* 86661*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::FP_TO_UINT),// ->86825
gen/lib/Target/X86/X86GenFastISel.inc 5918 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/TargetLowering.h 970 case ISD::STRICT_FP_TO_UINT: EqOpc = ISD::FP_TO_UINT; break;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1574 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
12816 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT &&
12997 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2521 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2522 OpToUse = ISD::FP_TO_UINT;
2907 case ISD::FP_TO_UINT:
4179 case ISD::FP_TO_UINT:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 845 case ISD::FP_TO_UINT: Res = SoftenFloatOp_FP_TO_XINT(N); break;
1650 case ISD::FP_TO_UINT: Res = ExpandFloatOp_FP_TO_UINT(N); break;
1920 case ISD::FP_TO_UINT: R = PromoteFloatOp_FP_TO_XINT(N, OpNo); break;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 120 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
499 if (N->getOpcode() == ISD::FP_TO_UINT &&
500 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
526 return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
1700 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 402 case ISD::FP_TO_UINT:
528 case ISD::FP_TO_UINT:
605 if (NewOpc == ISD::FP_TO_UINT &&
615 Promoted = DAG.getNode(Op->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
786 case ISD::FP_TO_UINT:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 93 case ISD::FP_TO_UINT:
604 case ISD::FP_TO_UINT:
909 case ISD::FP_TO_UINT:
2014 case ISD::FP_TO_UINT:
2837 case ISD::FP_TO_UINT:
4166 case ISD::FP_TO_UINT:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4391 case ISD::FP_TO_UINT: {
4393 APSInt IntVal(VT.getSizeInBits(), Opcode == ISD::FP_TO_UINT);
4435 case ISD::FP_TO_UINT:
4486 case ISD::FP_TO_UINT:
7785 case ISD::STRICT_FP_TO_UINT: NewOpc = ISD::FP_TO_UINT; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3428 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 330 case ISD::FP_TO_UINT: return "fp_to_uint";
lib/CodeGen/TargetLoweringBase.cpp 1620 case FPToUI: return ISD::FP_TO_UINT;
lib/Target/AArch64/AArch64ISelLowering.cpp 264 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
265 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
266 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
596 setTargetDAGCombine(ISD::FP_TO_UINT);
689 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
870 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
3063 case ISD::FP_TO_UINT:
11733 case ISD::FP_TO_UINT:
12088 case ISD::FP_TO_UINT:
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 363 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
364 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
365 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
371 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
372 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
373 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 },
378 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
379 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 },
385 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
386 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 },
387 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 2 },
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 343 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
365 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
1155 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
1550 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1688 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2);
1689 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc);
2571 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2573 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
lib/Target/AMDGPU/R600ISelLowering.cpp 162 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
165 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
657 case ISD::FP_TO_UINT:
lib/Target/AMDGPU/SIISelLowering.cpp 475 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
493 setOperationAction(ISD::FP_TO_UINT, MVT::f16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 169 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
174 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
291 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
851 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
852 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
906 setTargetDAGCombine(ISD::FP_TO_UINT);
963 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
965 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
9168 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
14444 case ISD::FP_TO_UINT:
lib/Target/ARM/ARMTargetTransformInfo.cpp 263 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
265 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
267 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
281 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
283 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
285 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
298 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
300 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
302 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
304 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
306 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
308 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
310 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
312 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
314 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
316 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
lib/Target/Hexagon/HexagonISelLowering.cpp 1533 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1534 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1535 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
lib/Target/Mips/MipsISelLowering.cpp 413 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
414 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
lib/Target/Mips/MipsSEISelLowering.cpp 356 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
1928 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
lib/Target/PowerPC/PPCISelLowering.cpp 233 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
503 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
508 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
515 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
517 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
524 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
530 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
699 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
837 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
957 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
1005 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
7465 if (Op.getOpcode() == ISD::FP_TO_UINT) {
7511 (Op.getOpcode() == ISD::FP_TO_UINT ||
8215 (V->getOperand(i).getOpcode() == ISD::FP_TO_UINT &&
10143 case ISD::FP_TO_UINT:
10234 case ISD::FP_TO_UINT:
12697 Opcode = ISD::FP_TO_UINT;
13086 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
13259 assert((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT)
13421 if (Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT) {
lib/Target/Sparc/SparcISelLowering.cpp 1515 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1517 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
3023 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
3347 case ISD::FP_TO_UINT:
lib/Target/SystemZ/SystemZISelLowering.cpp 208 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
384 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
385 setOperationAction(ISD::FP_TO_UINT, MVT::v2f64, Legal);
400 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
401 setOperationAction(ISD::FP_TO_UINT, MVT::v4f32, Legal);
lib/Target/X86/X86ISelDAGToDAG.cpp 808 case ISD::FP_TO_UINT: {
818 case ISD::FP_TO_UINT: NewOpc = X86ISD::CVTTP2UI; break;
lib/Target/X86/X86ISelLowering.cpp 278 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
279 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
280 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
283 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
284 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
774 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
943 setOperationAction(ISD::FP_TO_UINT, MVT::v2i8, Custom);
944 setOperationAction(ISD::FP_TO_UINT, MVT::v4i8, Custom);
945 setOperationAction(ISD::FP_TO_UINT, MVT::v8i8, Custom);
946 setOperationAction(ISD::FP_TO_UINT, MVT::v2i16, Custom);
947 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
1121 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i16, MVT::v8i32);
1303 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1305 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v4i1, MVT::v4i32);
1307 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Custom);
1382 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1383 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v16i1, MVT::v16i32);
1384 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v16i8, MVT::v16i32);
1385 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v16i16, MVT::v16i32);
1474 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1537 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1538 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1539 setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
1569 setOperationAction(ISD::FP_TO_UINT, VT, Legal);
1747 setOperationAction(ISD::FP_TO_UINT, MVT::v2f32, Custom);
19541 Opc = ISD::FP_TO_UINT;
27703 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
28117 case ISD::FP_TO_UINT: {
28136 Res = DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
lib/Target/X86/X86TargetTransformInfo.cpp 1323 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 },
1324 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 },
1325 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 },
1326 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
1327 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 },
1328 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 },
1393 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 },
1394 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 },
1396 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
1397 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
1398 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 },
1399 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 },
1400 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 },
1401 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 },
1402 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 },
1403 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 },
1404 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 },
1510 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 },
1511 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 },
1582 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 },
1583 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 },