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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc105696 /*236394*/ /*SwitchOpcode*/ 68, TARGET_VAL(ISD::FP_ROUND),// ->236465
109430 /*244449*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::FP_ROUND),// ->244484
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4282 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc73393 /*162114*/ /*SwitchOpcode*/ 20|128,1/*148*/, TARGET_VAL(ISD::FP_ROUND),// ->162266
74684 /*165276*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_ROUND),
74695 /*165294*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_ROUND),
74737 /*165402*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_ROUND),
77194 /*171620*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_ROUND),
77239 /*171728*/ /*SwitchOpcode*/ 103, TARGET_VAL(ISD::FP_ROUND),// ->171834
gen/lib/Target/ARM/ARMGenDAGISel.inc44909 /* 99348*/ /*SwitchOpcode*/ 88, TARGET_VAL(ISD::FP_ROUND),// ->99439
gen/lib/Target/ARM/ARMGenFastISel.inc 2717 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68332 /*132302*/ /*SwitchOpcode*/ 8, TARGET_VAL(ISD::FP_ROUND),// ->132313
gen/lib/Target/Mips/MipsGenDAGISel.inc27805 /* 52594*/ /*SwitchOpcode*/ 75, TARGET_VAL(ISD::FP_ROUND),// ->52672
gen/lib/Target/Mips/MipsGenFastISel.inc 1203 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc71195 /*150141*/ /*SwitchOpcode*/ 65, TARGET_VAL(ISD::FP_ROUND),// ->150209
gen/lib/Target/PowerPC/PPCGenDAGISel.inc34613 /* 89264*/ /*SwitchOpcode*/ 20|128,1/*148*/, TARGET_VAL(ISD::FP_ROUND),// ->89416
40721 /*102349*/ /*SwitchOpcode*/ 28|128,1/*156*/, TARGET_VAL(ISD::FP_ROUND),// ->102509
40730 /*102365*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_ROUND),
40738 /*102379*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_ROUND),
40747 /*102394*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_ROUND),
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1705 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13650 /* 25560*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::FP_ROUND),// ->25608
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3135 /* 5790*/ /*SwitchOpcode*/ 40, TARGET_VAL(ISD::FP_ROUND),// ->5833
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc24175 /* 45544*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_ROUND),
25407 /* 48219*/ /*SwitchOpcode*/ 12|128,1/*140*/, TARGET_VAL(ISD::FP_ROUND),// ->48363
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18872 /* 36030*/ /*SwitchOpcode*/ 8, TARGET_VAL(ISD::FP_ROUND),// ->36041
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 970 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc71019 /*149821*/ /*SwitchOpcode*/ 48|128,2/*304*/, TARGET_VAL(ISD::FP_ROUND),// ->150129
132873 /*272643*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::FP_ROUND),// ->272719
139468 /*286330*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::FP_ROUND),// ->286404
142001 /*291080*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::FP_ROUND),// ->291100
144046 /*295074*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::FP_ROUND),// ->295093
166641 /*338004*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::FP_ROUND),// ->338080
172951 /*351134*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::FP_ROUND),// ->351208
174971 /*354976*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::FP_ROUND),// ->354996
176453 /*357911*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::FP_ROUND),// ->357930
237592 /*484796*/ /*SwitchOpcode*/ 47, TARGET_VAL(ISD::FP_ROUND),// ->484846
gen/lib/Target/X86/X86GenFastISel.inc 5916 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/TargetLowering.h 971 case ISD::STRICT_FP_ROUND: EqOpc = ISD::FP_ROUND; break;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1575 case ISD::FP_ROUND: return visitFP_ROUND(N);
9240 CastOpcode == ISD::FP_ROUND) &&
9266 if (CastOpcode == ISD::FP_ROUND) {
12571 } else if (N1.getOpcode() == ISD::FP_ROUND &&
12575 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1));
12653 N1.getOpcode() == ISD::FP_ROUND)) {
13010 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
13017 if (N0.getOpcode() == ISD::FP_ROUND) {
13038 return DAG.getNode(ISD::FP_ROUND, DL, VT, N0.getOperand(0),
13045 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
13064 N->use_begin()->getOpcode() == ISD::FP_ROUND)
13078 if (N0.getOpcode() == ISD::FP_ROUND
13083 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
13098 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
16291 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2827 case ISD::FP_ROUND:
3152 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
4289 TruncOp = ISD::FP_ROUND;
4298 if (TruncOp != ISD::FP_ROUND)
4358 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4366 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4382 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4404 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 87 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break;
843 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break;
898 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16);
1026 Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(),
1648 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break;
1743 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
2090 case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break;
2324 DAG.getNode(ISD::FP_ROUND, DL, VT, NV, DAG.getIntPtrConstant(0, DL)));
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 428 case ISD::FP_ROUND:
564 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
325 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
631 case ISD::FP_ROUND:
790 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
905 case ISD::FP_ROUND:
1747 if (N->getOpcode() == ISD::FP_ROUND) {
1989 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
2620 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
2672 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2673 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
2835 case ISD::FP_ROUND:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 1101 : getNode(ISD::FP_ROUND, DL, VT, Op, getIntPtrConstant(0, DL));
4031 case ISD::FP_ROUND: {
4471 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node");
5010 if (N1CFP && Opcode == ISD::FP_ROUND) {
5165 case ISD::FP_ROUND:
7782 case ISD::STRICT_FP_ROUND: NewOpc = ISD::FP_ROUND; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 321 ISD::FP_ROUND, DL, ValueVT, Val,
3410 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
6168 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 320 case ISD::FP_ROUND: return "fp_round";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 5449 case ISD::FP_ROUND:
5571 case ISD::FP_ROUND:
5572 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
lib/CodeGen/TargetLoweringBase.cpp 1624 case FPTrunc: return ISD::FP_ROUND;
lib/Target/AArch64/AArch64ISelLowering.cpp 273 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
274 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
426 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
432 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
692 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
2518 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
2542 ISD::FP_ROUND, dl, MVT::f16,
3016 case ISD::FP_ROUND:
4823 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL));
5496 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 2512 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2539 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
3798 case ISD::FP_ROUND: {
3803 return DAG.getNode(ISD::FP_ROUND, SL, VT,
3812 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
lib/Target/AMDGPU/R600ISelLowering.cpp 275 setTargetDAGCombine(ISD::FP_ROUND);
1858 case ISD::FP_ROUND: {
lib/Target/AMDGPU/SIISelLowering.cpp 214 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
489 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
4052 case ISD::FP_ROUND:
7624 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag);
8572 case ISD::FP_ROUND:
8743 case ISD::FP_ROUND:
lib/Target/ARM/ARMISelLowering.cpp 856 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
966 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
972 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
979 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
9235 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
lib/Target/ARM/ARMTargetTransformInfo.cpp 156 { ISD::FP_ROUND, MVT::v2f64, 2 },
161 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
lib/Target/PowerPC/PPCISelLowering.cpp 907 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
908 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
959 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
7726 Value = DAG.getNode(ISD::FP_ROUND, dl,
7876 FP = DAG.getNode(ISD::FP_ROUND, dl,
7949 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
8211 (V->getOperand(i).getOpcode() == ISD::FP_ROUND &&
12683 SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl,
12728 if (FirstInput.getOpcode() == ISD::FP_ROUND &&
12740 if (IsRoundOfExtLoad && N->getOperand(i).getOpcode() != ISD::FP_ROUND)
13106 FP = DAG.getNode(ISD::FP_ROUND, dl,
13754 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
lib/Target/Sparc/SparcISelLowering.cpp 1717 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1745 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1746 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
3051 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
lib/Target/SystemZ/SystemZISelLowering.cpp 614 setTargetDAGCombine(ISD::FP_ROUND);
5764 if (OtherRound.getOpcode() == ISD::FP_ROUND &&
6168 case ISD::FP_ROUND: return combineFP_ROUND(N, DCI);
lib/Target/X86/X86ISelDAGToDAG.cpp 989 case ISD::FP_ROUND:
1021 if (N->getOpcode() == ISD::FP_ROUND)
lib/Target/X86/X86ISelLowering.cpp 691 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
695 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
699 setOperationAction(ISD::FP_ROUND, MVT::f80, Custom);
966 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
2884 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
18893 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
19812 Sign = DAG.getNode(ISD::FP_ROUND, dl, VT, Sign, DAG.getIntPtrConstant(1, dl));
27705 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
28239 case ISD::FP_ROUND: {
lib/Target/X86/X86TargetTransformInfo.cpp 1337 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 },
1433 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 },
1514 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 },