reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

74303 /*164367*/  /*SwitchOpcode*/ 79|128,1/*207*/, TARGET_VAL(ISD::FP16_TO_FP),// ->164578

gen/lib/Target/AMDGPU/R600GenDAGISel.inc

10376 /* 39555*/  /*SwitchOpcode*/ 71, TARGET_VAL(ISD::FP16_TO_FP),// ->39629

gen/lib/Target/ARM/ARMGenDAGISel.inc

45259 /*100168*/  /*SwitchOpcode*/ 63, TARGET_VAL(ISD::FP16_TO_FP),// ->100234

gen/lib/Target/X86/X86GenDAGISel.inc

75205 /*158640*/  /*SwitchOpcode*/ 61|128,1/*189*/, TARGET_VAL(ISD::FP16_TO_FP),// ->158833

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1604   case ISD::FP16_TO_FP:         return visitFP16_TO_FP(N);
13072   if (N0.getOpcode() == ISD::FP16_TO_FP &&
13073       TLI.getOperationAction(ISD::FP16_TO_FP, VT) == TargetLowering::Legal)
13074     return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), VT, N0.getOperand(0));
19390   if (N0->getOpcode() == ISD::FP16_TO_FP)
19403       return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), N->getValueType(0),

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

  913           Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
 3132   case ISD::FP16_TO_FP:
 3138           DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
 4034   case ISD::FP16_TO_FP:

lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

   88     case ISD::FP16_TO_FP:  R = SoftenFloatRes_FP16_TO_FP(N); break;
  883     return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), RVT, Op);
 1886       return ISD::FP16_TO_FP;
 2038     case ISD::FP16_TO_FP:

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 1189   case ISD::FP16_TO_FP:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 4340     case ISD::FP16_TO_FP: {

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  334   case ISD::FP16_TO_FP:                 return "fp16_to_fp";

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  301   setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
 3814   case ISD::FP16_TO_FP: {
 3826     return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg);
 3842   case ISD::FP16_TO_FP: {
 3851     return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);

lib/Target/AMDGPU/SIISelLowering.cpp

  469     setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote);
  470     AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);

lib/Target/ARM/ARMISelLowering.cpp

 1323       setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
 1329       setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);

lib/Target/Mips/MipsISelLowering.cpp

  454   setOperationAction(ISD::FP16_TO_FP,        MVT::f32,   Expand);
  456   setOperationAction(ISD::FP16_TO_FP,        MVT::f64,   Expand);

lib/Target/RISCV/RISCVISelLowering.cpp

  149       ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  104     setOperationAction(ISD::FP16_TO_FP, T, Expand);

lib/Target/X86/X86ISelLowering.cpp

  374     setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
  379   setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
  380   setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
  381   setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);