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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc74292 /*176411*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
74471 /*176745*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
93917 /*213522*/ OPC_SwitchOpcode /*5 cases */, 71|128,1/*199*/, TARGET_VAL(ISD::FMUL),// ->213726
94229 /*214100*/ OPC_SwitchOpcode /*5 cases */, 71|128,1/*199*/, TARGET_VAL(ISD::FMUL),// ->214304
104968 /*234971*/ /*SwitchOpcode*/ 42|128,6/*810*/, TARGET_VAL(ISD::FMUL),// ->235785
105398 /*235831*/ OPC_SwitchOpcode /*2 cases */, 41, TARGET_VAL(ISD::FMUL),// ->235876
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7729 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc75606 /*167775*/ /*SwitchOpcode*/ 76|128,1/*204*/, TARGET_VAL(ISD::FMUL),// ->167983
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 9523 /* 36307*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::FMUL),// ->36414
gen/lib/Target/ARM/ARMGenDAGISel.inc41483 /* 91202*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
41551 /* 91356*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
41615 /* 91503*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
41650 /* 91582*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
41683 /* 91659*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
41718 /* 91738*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
41769 /* 91858*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
41797 /* 91917*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
41881 /* 92190*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42027 /* 92634*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42088 /* 92758*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42141 /* 92858*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42166 /* 92907*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42219 /* 93008*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42279 /* 93138*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42342 /* 93270*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42398 /* 93385*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42447 /* 93477*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42470 /* 93522*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42519 /* 93615*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42580 /* 93760*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42643 /* 93906*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42684 /* 94002*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42791 /* 94256*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42838 /* 94360*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42871 /* 94437*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42908 /* 94518*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42941 /* 94595*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
42986 /* 94697*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
43019 /* 94774*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
43055 /* 94857*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
43198 /* 95297*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
43832 /* 96737*/ /*SwitchOpcode*/ 65, TARGET_VAL(ISD::FMUL),// ->96805
44003 /* 97173*/ /*SwitchOpcode*/ 111|128,9/*1263*/, TARGET_VAL(ISD::FMUL),// ->98440
gen/lib/Target/ARM/ARMGenFastISel.inc 5169 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68478 /*132623*/ /*SwitchOpcode*/ 12, TARGET_VAL(ISD::FMUL),// ->132638
gen/lib/Target/Mips/MipsGenDAGISel.inc26727 /* 50601*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
26757 /* 50655*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
26786 /* 50710*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
26814 /* 50762*/ /*SwitchOpcode*/ 47, TARGET_VAL(ISD::FMUL),// ->50812
26894 /* 50908*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
26934 /* 50988*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
26978 /* 51069*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
27021 /* 51151*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
27116 /* 51320*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
27146 /* 51376*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
27222 /* 51516*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
27242 /* 51553*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
27525 /* 52086*/ /*SwitchOpcode*/ 63|128,1/*191*/, TARGET_VAL(ISD::FMUL),// ->52281
gen/lib/Target/Mips/MipsGenFastISel.inc 3412 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc70450 /*148597*/ /*SwitchOpcode*/ 112|128,2/*368*/, TARGET_VAL(ISD::FMUL),// ->148969
gen/lib/Target/PowerPC/PPCGenDAGISel.inc37924 /* 96468*/ /*SwitchOpcode*/ 44|128,1/*172*/, TARGET_VAL(ISD::FMUL),// ->96644
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3241 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13494 /* 25239*/ /*SwitchOpcode*/ 102, TARGET_VAL(ISD::FMUL),// ->25344
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3016 /* 5578*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::FMUL),// ->5674
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc22744 /* 42824*/ /*SwitchOpcode*/ 8|128,4/*520*/, TARGET_VAL(ISD::FMUL),// ->43348
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18930 /* 36143*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::FMUL),// ->36194
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1909 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc63573 /*134327*/ /*SwitchOpcode*/ 89|128,15/*2009*/, TARGET_VAL(ISD::FMUL),// ->136340
130585 /*268136*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::FMUL),// ->268410
136184 /*279392*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::FMUL),// ->279662
141611 /*290362*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FMUL),// ->290399
143506 /*293953*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FMUL),// ->293990
149938 /*306154*/ /*SwitchOpcode*/ 29|128,1/*157*/, TARGET_VAL(ISD::FMUL),// ->306315
153260 /*312490*/ /*SwitchOpcode*/ 25|128,1/*153*/, TARGET_VAL(ISD::FMUL),// ->312647
156646 /*318937*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::FMUL),// ->318959
157931 /*321286*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::FMUL),// ->321307
164379 /*333553*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::FMUL),// ->333827
169691 /*344252*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::FMUL),// ->344522
174627 /*354339*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FMUL),// ->354376
175953 /*356869*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FMUL),// ->356906
181019 /*366651*/ /*SwitchOpcode*/ 52|128,2/*308*/, TARGET_VAL(ISD::FMUL),// ->366963
185475 /*375159*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::FMUL),// ->375181
186181 /*376437*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::FMUL),// ->376458
233606 /*476377*/ /*SwitchOpcode*/ 59|128,1/*187*/, TARGET_VAL(ISD::FMUL),// ->476568
235082 /*479481*/ /*SwitchOpcode*/ 43|128,1/*171*/, TARGET_VAL(ISD::FMUL),// ->479656
236762 /*483000*/ /*SwitchOpcode*/ 66|128,1/*194*/, TARGET_VAL(ISD::FMUL),// ->483198
237765 /*485155*/ /*SwitchOpcode*/ 40|128,1/*168*/, TARGET_VAL(ISD::FMUL),// ->485327
240038 /*489907*/ /*SwitchOpcode*/ 59|128,1/*187*/, TARGET_VAL(ISD::FMUL),// ->490098
241514 /*493011*/ /*SwitchOpcode*/ 43|128,1/*171*/, TARGET_VAL(ISD::FMUL),// ->493186
243279 /*496707*/ /*SwitchOpcode*/ 66|128,1/*194*/, TARGET_VAL(ISD::FMUL),// ->496905
244283 /*498864*/ /*SwitchOpcode*/ 40|128,1/*168*/, TARGET_VAL(ISD::FMUL),// ->499036
gen/lib/Target/X86/X86GenFastISel.inc13515 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/TargetLowering.h 943 case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
2272 case ISD::FMUL:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1564 case ISD::FMUL: return visitFMUL(N);
11363 if (N.getOpcode() != ISD::FMUL)
11421 N0.getOperand(2).getOpcode() == ISD::FMUL &&
11434 N1.getOperand(2).getOpcode() == ISD::FMUL &&
11575 if (N.getOpcode() != ISD::FMUL)
11834 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation");
11966 if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL)
12016 if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) {
12017 if (N0.getOpcode() == ISD::FMUL) {
12025 return DAG.getNode(ISD::FMUL, DL, VT, N1, NewCFP, Flags);
12034 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), NewCFP, Flags);
12038 if (N1.getOpcode() == ISD::FMUL) {
12046 return DAG.getNode(ISD::FMUL, DL, VT, N0, NewCFP, Flags);
12055 return DAG.getNode(ISD::FMUL, DL, VT, N1.getOperand(0), NewCFP, Flags);
12064 return DAG.getNode(ISD::FMUL, DL, VT,
12074 return DAG.getNode(ISD::FMUL, DL, VT,
12084 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0),
12209 return DAG.getNode(ISD::FMUL, DL, VT, N0, N1, Flags);
12214 return DAG.getNode(ISD::FMUL, DL, VT, N1, N0, Flags);
12229 N0.getOpcode() == ISD::FMUL) {
12236 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, N01, N1, Flags);
12237 return DAG.getNode(ISD::FMUL, DL, VT, N00, MulConsts, Flags);
12246 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, Two, N1, Flags);
12247 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), MulConsts, Flags);
12266 return DAG.getNode(ISD::FMUL, DL, VT, NegN0, NegN1, Flags);
12373 if (N2.getOpcode() == ISD::FMUL && N0 == N2.getOperand(0) &&
12376 return DAG.getNode(ISD::FMUL, DL, VT, N0,
12382 if (N0.getOpcode() == ISD::FMUL &&
12387 DAG.getNode(ISD::FMUL, DL, VT, N1, N0.getOperand(1),
12421 return DAG.getNode(ISD::FMUL, DL, VT, N0,
12429 return DAG.getNode(ISD::FMUL, DL, VT, N0,
12501 SDValue NewNode = DAG.getNode(ISD::FMUL, SDLoc(U), VT, Dividend,
12554 return DAG.getNode(ISD::FMUL, DL, VT, N0,
12562 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);
12569 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);
12577 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);
12579 } else if (N1.getOpcode() == ISD::FMUL) {
12597 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);
12782 return DAG.getNode(ISD::FMUL, DL, VT, Sqrt, SqrtSqrt, Flags);
13196 if (N0.getOpcode() == ISD::FMUL &&
13206 ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
20297 MulEst = DAG.getNode(ISD::FMUL, DL, VT, N, Est, Flags);
20301 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Op, MulEst, Flags);
20308 NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags);
20316 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, N, Flags);
20341 SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg, Flags);
20346 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est, Flags);
20347 NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst, Flags);
20349 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags);
20354 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Arg, Flags);
20379 SDValue AE = DAG.getNode(ISD::FMUL, DL, VT, Arg, Est, Flags);
20380 SDValue AEE = DAG.getNode(ISD::FMUL, DL, VT, AE, Est, Flags);
20389 LHS = DAG.getNode(ISD::FMUL, DL, VT, Est, MinusHalf, Flags);
20392 LHS = DAG.getNode(ISD::FMUL, DL, VT, AE, MinusHalf, Flags);
20395 Est = DAG.getNode(ISD::FMUL, DL, VT, LHS, RHS, Flags);
lib/CodeGen/SelectionDAG/FastISel.cpp 1809 return selectBinaryOp(I, ISD::FMUL);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 4029 case ISD::FMUL:
4348 case ISD::FMUL:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 83 case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break;
1156 case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break;
2080 case ISD::FMUL:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 372 case ISD::FMUL:
1240 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 113 case ISD::FMUL:
936 case ISD::FMUL:
2123 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break;
2756 case ISD::FMUL:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3999 case ISD::FMUL:
4995 case ISD::FMUL:
5023 case ISD::FMUL:
5121 case ISD::FMUL:
7173 if (Opcode == ISD::FMUL || Opcode == ISD::FDIV)
7756 case ISD::STRICT_FMUL: NewOpc = ISD::FMUL; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 4922 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4926 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4938 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4942 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4945 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4959 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4963 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4966 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4969 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4972 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4975 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4999 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
5021 DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
5037 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5041 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5054 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5058 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5061 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5064 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5079 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5083 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5086 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5089 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5092 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5095 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
5133 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5137 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5150 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5154 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5157 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5160 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5176 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5180 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5183 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5186 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5189 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5192 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
5216 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
5232 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5236 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5248 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5252 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5255 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5269 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
5273 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
5276 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
5279 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
5282 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
5326 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
5367 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
5372 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
6154 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
8923 Res = DAG.getNode(ISD::FMUL, dl, VT, Op1,
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 679 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 250 case ISD::FMUL: return "fmul";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 2483 case ISD::FMUL:
5412 case ISD::FMUL:
5421 if (C->isExactlyValue(2.0) && Op.getOpcode() == ISD::FMUL)
5519 case ISD::FMUL:
7322 case ISD::VECREDUCE_FMUL: BaseOpcode = ISD::FMUL; break;
lib/CodeGen/TargetLoweringBase.cpp 1597 case FMul: return ISD::FMUL;
lib/Target/AArch64/AArch64ISelLowering.cpp 243 setOperationAction(ISD::FMUL, MVT::f128, Custom);
403 setOperationAction(ISD::FMUL, MVT::f16, Promote);
423 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
429 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
457 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
670 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
3012 case ISD::FMUL:
5789 SDValue Step = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Estimate,
5792 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Step, Flags);
5800 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Operand, Estimate, Flags);
5830 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Step, Flags);
9573 Op.getOpcode() != ISD::FMUL)
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 419 setOperationAction(ISD::FMUL, VT, Expand);
518 case ISD::FMUL:
1578 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1680 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,
1682 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1,
2028 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
2293 return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand);
2303 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags());
2564 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
3518 if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL)
3681 case ISD::FMUL:
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp 393 case ISD::FMUL:
lib/Target/AMDGPU/R600ISelLowering.cpp 765 DAG.getNode(ISD::FMUL, DL, VT, Arg,
785 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal,
lib/Target/AMDGPU/SIISelLowering.cpp 610 setOperationAction(ISD::FMUL, MVT::v2f16, Legal);
637 setOperationAction(ISD::FMUL, MVT::v4f16, Custom);
4078 case ISD::FMUL:
7562 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, Flags);
7579 case ISD::FMUL:
7621 SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, CvtSrc0, RcpSrc1);
7653 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
7658 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
7660 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
7737 SDValue Mul = getFPBinOp(DAG, ISD::FMUL, SL, MVT::f32, NumeratorScaled,
7806 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
7956 SDValue MulVal = DAG.getNode(ISD::FMUL, DL, VT, Arg, OneOver2Pi);
7959 TrigVal = DAG.getNode(ISD::FMUL, DL, VT, Arg, OneOver2Pi);
8566 case ISD::FMUL:
8735 case ISD::FMUL:
9285 case ISD::FMUL:
lib/Target/ARM/ARMFastISel.cpp 1818 case ISD::FMUL:
2855 return SelectBinaryFPOp(I, ISD::FMUL);
lib/Target/ARM/ARMISelLowering.cpp 765 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
938 setOperationAction(ISD::FMUL, MVT::f64, Expand);
8518 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
8551 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
8556 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
8660 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
8664 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
8669 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
13481 Op.getOpcode() != ISD::FMUL)
lib/Target/Hexagon/HexagonISelLowering.cpp 1427 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1528 setOperationAction(ISD::FMUL, MVT::f64, Expand);
lib/Target/Mips/MipsSEISelLowering.cpp 133 setOperationAction(ISD::FMUL, MVT::f16, Promote);
392 setOperationAction(ISD::FMUL, Ty, Legal);
1894 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1907 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
lib/Target/NVPTX/NVPTXISelLowering.cpp 536 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
4368 else if (N0.getOpcode() == ISD::FMUL) {
lib/Target/PowerPC/PPCISelLowering.cpp 886 setOperationAction(ISD::FMUL, MVT::f128, Legal);
932 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
983 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
10076 case ISD::FMUL:
lib/Target/Sparc/SparcISelLowering.cpp 1713 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1738 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1796 setOperationAction(ISD::FMUL, MVT::f32, Promote);
3042 case ISD::FMUL: return LowerF128Op(Op, DAG,
lib/Target/SystemZ/SystemZISelLowering.cpp 475 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
507 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
lib/Target/X86/X86ISelLowering.cpp 674 setOperationAction(ISD::FMUL, MVT::f128, Custom);
8881 if (Opnd0.getOpcode() != ISD::FMUL ||
18672 fHI = DAG.getNode(ISD::FMUL, DL, MVT::v2f64, fHI, TWOHW);
27711 case ISD::FMUL: return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
33591 if (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL || Opcode1 == ISD::FSUB ||
33596 (N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) {
36228 case ISD::FMUL:
41559 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
lib/Target/X86/X86IntrinsicsInfo.h 819 X86_INTRINSIC_DATA(avx512_mul_pd_512, INTR_TYPE_2OP, ISD::FMUL, X86ISD::FMUL_RND),
820 X86_INTRINSIC_DATA(avx512_mul_ps_512, INTR_TYPE_2OP, ISD::FMUL, X86ISD::FMUL_RND),
lib/Target/X86/X86TargetTransformInfo.cpp 200 { ISD::FMUL, MVT::f64, 2 }, // mulsd
201 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd
202 { ISD::FMUL, MVT::v4f32, 2 }, // mulps
544 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
548 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
698 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
699 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
761 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
762 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
763 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
764 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/