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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc106272 /*237463*/ /*SwitchOpcode*/ 110, TARGET_VAL(ISD::FMINNUM),// ->237576
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7728 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc63833 /*139405*/ /*SwitchOpcode*/ 35|128,1/*163*/, TARGET_VAL(ISD::FMINNUM),// ->139572
64310 /*140547*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
64600 /*141217*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
64665 /*141373*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
64730 /*141529*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
64796 /*141688*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
65435 /*143191*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
65739 /*143889*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
65807 /*144051*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
65875 /*144213*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
65943 /*144375*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
66001 /*144522*/ /*SwitchOpcode*/ 116|128,43/*5620*/, TARGET_VAL(ISD::FMINNUM),// ->150146
66071 /*144703*/ /*SwitchOpcode*/ 35|128,1/*163*/, TARGET_VAL(ISD::FMINNUM),// ->144870
66679 /*146160*/ /*SwitchOpcode*/ 70|128,2/*326*/, TARGET_VAL(ISD::FMINNUM),// ->146490
66832 /*146508*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
66898 /*146667*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
66957 /*146814*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
67109 /*147160*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
67174 /*147316*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
67798 /*148797*/ /*SwitchOpcode*/ 84|128,2/*340*/, TARGET_VAL(ISD::FMINNUM),// ->149141
67958 /*149159*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
68027 /*149324*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
68089 /*149477*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
68248 /*149837*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
68316 /*149999*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
68666 /*150871*/ /*SwitchOpcode*/ 35|128,1/*163*/, TARGET_VAL(ISD::FMINNUM),// ->151038
69143 /*152013*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
69433 /*152683*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
69498 /*152839*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
69563 /*152995*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
69629 /*153154*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
70268 /*154657*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
70572 /*155355*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
70640 /*155517*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
70708 /*155679*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
70776 /*155841*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
70834 /*155988*/ /*SwitchOpcode*/ 116|128,43/*5620*/, TARGET_VAL(ISD::FMINNUM),// ->161612
70904 /*156169*/ /*SwitchOpcode*/ 35|128,1/*163*/, TARGET_VAL(ISD::FMINNUM),// ->156336
71512 /*157626*/ /*SwitchOpcode*/ 70|128,2/*326*/, TARGET_VAL(ISD::FMINNUM),// ->157956
71665 /*157974*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
71731 /*158133*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
71790 /*158280*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
71942 /*158626*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
72007 /*158782*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
72631 /*160263*/ /*SwitchOpcode*/ 84|128,2/*340*/, TARGET_VAL(ISD::FMINNUM),// ->160607
72791 /*160625*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
72860 /*160790*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
72922 /*160943*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
73081 /*161303*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
73149 /*161465*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM),
75760 /*168191*/ /*SwitchOpcode*/ 76|128,1/*204*/, TARGET_VAL(ISD::FMINNUM),// ->168399
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 9631 /* 36735*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::FMINNUM),// ->36842
gen/lib/Target/ARM/ARMGenDAGISel.inc44802 /* 99107*/ /*SwitchOpcode*/ 18|128,1/*146*/, TARGET_VAL(ISD::FMINNUM),// ->99257
gen/lib/Target/ARM/ARMGenFastISel.inc 5168 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68486 /*132638*/ /*SwitchOpcode*/ 12, TARGET_VAL(ISD::FMINNUM),// ->132653
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc70652 /*148969*/ /*SwitchOpcode*/ 11|128,1/*139*/, TARGET_VAL(ISD::FMINNUM),// ->149112
gen/lib/Target/PowerPC/PPCGenDAGISel.inc43847 /*109448*/ /*SwitchOpcode*/ 27|128,1/*155*/, TARGET_VAL(ISD::FMINNUM),// ->109607
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3239 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13355 /* 24954*/ /*SwitchOpcode*/ 28, TARGET_VAL(ISD::FMINNUM),// ->24985
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc25643 /* 48735*/ /*SwitchOpcode*/ 84, TARGET_VAL(ISD::FMINNUM),// ->48822
include/llvm/CodeGen/BasicTTIImpl.h 1239 ISDs.push_back(ISD::FMINNUM);
include/llvm/CodeGen/TargetLowering.h 962 case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break;
2282 case ISD::FMINNUM:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1580 case ISD::FMINNUM: return visitFMINNUM(N);
8153 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
8168 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3107 case ISD::FMINNUM:
3816 case ISD::FMINNUM:
4351 case ISD::FMINNUM:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 68 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break;
1141 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break;
2079 case ISD::FMINNUM:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 405 case ISD::FMINNUM:
814 case ISD::FMINNUM:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 114 case ISD::FMINNUM:
937 case ISD::FMINNUM:
2137 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
2740 case ISD::FMINNUM:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4058 case ISD::FMINNUM:
7775 case ISD::STRICT_FMINNUM: NewOpc = ISD::FMINNUM; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3296 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
3298 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
3299 Opc = ISD::FMINNUM;
3303 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
3304 ISD::FMINNUM : ISD::FMINIMUM;
6073 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
7586 if (visitBinaryFloatCall(I, ISD::FMINNUM))
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 182 case ISD::FMINNUM: return "fminnum";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 6122 unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ?
6149 Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM;
7336 BaseOpcode = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
lib/CodeGen/TargetLoweringBase.cpp 635 setOperationAction(ISD::FMINNUM, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 415 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
480 setOperationAction(ISD::FMINNUM, Ty, Legal);
497 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
884 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM})
10501 return DAG.getNode(ISD::FMINNUM, SDLoc(N), N->getValueType(0),
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 258 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
404 setOperationAction(ISD::FMINNUM, VT, Expand);
521 case ISD::FMINNUM:
3615 return ISD::FMINNUM;
3616 case ISD::FMINNUM:
3732 case ISD::FMINNUM:
lib/Target/AMDGPU/SIISelLowering.cpp 399 setOperationAction(ISD::FMINNUM, MVT::f32, Custom);
401 setOperationAction(ISD::FMINNUM, MVT::f64, Custom);
586 setOperationAction(ISD::FMINNUM, MVT::f16, Custom);
593 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand);
641 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom);
643 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
706 setTargetDAGCombine(ISD::FMINNUM);
4062 case ISD::FMINNUM:
5771 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
8594 case ISD::FMINNUM:
8778 case ISD::FMINNUM:
8974 if (SrcOpc == ISD::FMINNUM || SrcOpc == ISD::FMAXNUM) {
8999 case ISD::FMINNUM:
9169 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) ||
9292 case ISD::FMINNUM:
9954 case ISD::FMINNUM:
lib/Target/ARM/ARMISelLowering.cpp 328 setOperationAction(ISD::FMINNUM, VT, Legal);
707 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
1349 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1352 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1354 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1365 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1401 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1403 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
3714 ? ISD::FMINNUM : ISD::FMAXNUM;
lib/Target/Hexagon/HexagonISelLowering.cpp 1432 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
1530 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
lib/Target/Mips/MipsSEISelLowering.cpp 158 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
lib/Target/NVPTX/NVPTXISelLowering.cpp 572 ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) {
578 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
lib/Target/PowerPC/PPCISelLowering.cpp 583 setOperationAction(ISD::FMINNUM, VT, Legal);
973 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
1018 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
lib/Target/PowerPC/PPCTargetTransformInfo.cpp 340 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break;
406 Opcode = ISD::FMINNUM; break;
lib/Target/RISCV/RISCVISelLowering.cpp 153 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
170 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
lib/Target/SystemZ/SystemZISelLowering.cpp 521 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
526 setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal);
531 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
536 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
541 setOperationAction(ISD::FMINNUM, MVT::f128, Legal);
lib/Target/X86/X86ISelLowering.cpp 724 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
1856 setTargetDAGCombine(ISD::FMINNUM);
36232 case ISD::FMINNUM:
44946 case ISD::FMINNUM:
lib/Target/X86/X86TargetTransformInfo.cpp 2695 ISD = ISD::FMINNUM;
2702 {ISD::FMINNUM, MVT::v4f32, 4},
2706 {ISD::FMINNUM, MVT::v2f64, 3},
2718 {ISD::FMINNUM, MVT::v4f32, 2},
2735 {ISD::FMINNUM, MVT::v4f32, 1},
2736 {ISD::FMINNUM, MVT::v4f64, 1},
2737 {ISD::FMINNUM, MVT::v8f32, 2},
2768 {ISD::FMINNUM, MVT::v8f64, 1},
2769 {ISD::FMINNUM, MVT::v16f32, 2},
2777 {ISD::FMINNUM, MVT::v4f32, 4},
2781 {ISD::FMINNUM, MVT::v2f64, 3},
2793 {ISD::FMINNUM, MVT::v4f32, 3},
2810 {ISD::FMINNUM, MVT::v4f32, 1},
2811 {ISD::FMINNUM, MVT::v4f64, 1},
2812 {ISD::FMINNUM, MVT::v8f32, 1},
2843 {ISD::FMINNUM, MVT::v8f64, 1},
2844 {ISD::FMINNUM, MVT::v16f32, 2},