reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

76117 /*169003*/  /*SwitchOpcode*/ 35, TARGET_VAL(ISD::FEXP2),// ->169041

gen/lib/Target/AMDGPU/R600GenDAGISel.inc

 9883 /* 37761*/  /*SwitchOpcode*/ 78|128,1/*206*/, TARGET_VAL(ISD::FEXP2),// ->37971

gen/lib/Target/Mips/MipsGenDAGISel.inc

27579 /* 52185*/        OPC_CheckOpcode, TARGET_VAL(ISD::FEXP2),
27598 /* 52219*/      OPC_CheckOpcode, TARGET_VAL(ISD::FEXP2),
29751 /* 56644*/  /*SwitchOpcode*/ 25, TARGET_VAL(ISD::FEXP2),// ->56672

gen/lib/Target/Mips/MipsGenFastISel.inc

 1199   case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0, Op0IsKill);

include/llvm/CodeGen/BasicTTIImpl.h

 1221       ISDs.push_back(ISD::FEXP2);

include/llvm/CodeGen/TargetLowering.h

  953       case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 3907   case ISD::FEXP2:
 4401   case ISD::FEXP2:

lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

   77     case ISD::FEXP2:       R = SoftenFloatRes_FEXP2(N); break;
 1150   case ISD::FEXP2:      ExpandFloatRes_FEXP2(N, Lo, Hi); break;
 2059     case ISD::FEXP2:

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

  421   case ISD::FEXP2:

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

   84   case ISD::FEXP2:
  896   case ISD::FEXP2:
 2857   case ISD::FEXP2:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 4011   case ISD::FEXP2:
 7766   case ISD::STRICT_FEXP2:      NewOpc = ISD::FEXP2;      break;

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 5303   return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
 7661         if (visitUnaryFloatCall(I, ISD::FEXP2))

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  213   case ISD::FEXP2:                      return "fexp2";

lib/CodeGen/TargetLoweringBase.cpp

  771     setOperationAction(ISD::FEXP2,      VT, Expand);

lib/Target/AArch64/AArch64ISelLowering.cpp

  383   setOperationAction(ISD::FEXP2,   MVT::f16,   Promote);
  384   setOperationAction(ISD::FEXP2,   MVT::v4f16, Expand);
  385   setOperationAction(ISD::FEXP2,   MVT::v8f16, Expand);
  835     setOperationAction(ISD::FEXP2, VT, Expand);

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  251   setOperationAction(ISD::FEXP2,  MVT::f32, Legal);
  410     setOperationAction(ISD::FEXP2, VT, Expand);
 2304   return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags());

lib/Target/AMDGPU/SIISelLowering.cpp

 8587   case ISD::FEXP2:

lib/Target/ARM/ARMISelLowering.cpp

  343       setOperationAction(ISD::FEXP2, VT, Expand);
  788     setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
  809     setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
  825     setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
  954     setOperationAction(ISD::FEXP2,      MVT::f64, Expand);
 1380     setOperationAction(ISD::FEXP2, MVT::f16, Promote);

lib/Target/Hexagon/HexagonISelLowering.cpp

 1430     ISD::FLOG10,  ISD::FEXP,    ISD::FEXP2,   ISD::FCEIL,   ISD::FTRUNC,

lib/Target/Mips/MipsSEISelLowering.cpp

  152     setOperationAction(ISD::FEXP2, MVT::f16, Promote);
  389     setOperationAction(ISD::FEXP2, Ty, Legal);
 1895         DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));

lib/Target/PowerPC/PPCISelLowering.cpp

  637       setOperationAction(ISD::FEXP2, VT, Expand);
  971     setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
 1016     setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  186                     ISD::FEXP, ISD::FEXP2, ISD::FRINT}) {

lib/Target/X86/X86ISelLowering.cpp

  723   setOperationAction(ISD::FEXP2, MVT::f80, Expand);
  740     setOperationAction(ISD::FEXP2,     VT, Expand);