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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc104652 /*234350*/ /*SwitchOpcode*/ 29|128,2/*285*/, TARGET_VAL(ISD::FADD),// ->234639
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7723 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc58259 /*127706*/ OPC_CheckOpcode, TARGET_VAL(ISD::FADD),
74101 /*163853*/ /*SwitchOpcode*/ 26|128,2/*282*/, TARGET_VAL(ISD::FADD),// ->164139
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 9496 /* 36200*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::FADD),// ->36307
gen/lib/Target/ARM/ARMGenDAGISel.inc41478 /* 91190*/ /*SwitchOpcode*/ 104|128,23/*3048*/, TARGET_VAL(ISD::FADD),// ->94242
gen/lib/Target/ARM/ARMGenFastISel.inc 5163 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68448 /*132565*/ /*SwitchOpcode*/ 26, TARGET_VAL(ISD::FADD),// ->132594
gen/lib/Target/Mips/MipsGenDAGISel.inc26724 /* 50594*/ OPC_SwitchOpcode /*2 cases */, 108, TARGET_VAL(ISD::FADD),// ->50706
26931 /* 50980*/ OPC_SwitchOpcode /*2 cases */, 34|128,1/*162*/, TARGET_VAL(ISD::FADD),// ->51147
27113 /* 51313*/ /*SwitchOpcode*/ 45|128,2/*301*/, TARGET_VAL(ISD::FADD),// ->51618
gen/lib/Target/Mips/MipsGenFastISel.inc 3410 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc70097 /*147949*/ /*SwitchOpcode*/ 112|128,2/*368*/, TARGET_VAL(ISD::FADD),// ->148321
gen/lib/Target/PowerPC/PPCGenDAGISel.inc37842 /* 96313*/ /*SwitchOpcode*/ 23|128,1/*151*/, TARGET_VAL(ISD::FADD),// ->96468
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3235 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13394 /* 25029*/ /*SwitchOpcode*/ 102, TARGET_VAL(ISD::FADD),// ->25134
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3219 /* 5944*/ /*SwitchOpcode*/ 36, TARGET_VAL(ISD::FADD),// ->5983
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc23394 /* 44076*/ /*SwitchOpcode*/ 84|128,1/*212*/, TARGET_VAL(ISD::FADD),// ->44292
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18878 /* 36041*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::FADD),// ->36092
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1904 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc61832 /*130570*/ /*SwitchOpcode*/ 8|128,18/*2312*/, TARGET_VAL(ISD::FADD),// ->132886
130443 /*267862*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::FADD),// ->268136
136054 /*279122*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::FADD),// ->279392
141591 /*290325*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FADD),// ->290362
143488 /*293916*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FADD),// ->293953
149849 /*305993*/ /*SwitchOpcode*/ 29|128,1/*157*/, TARGET_VAL(ISD::FADD),// ->306154
153179 /*312333*/ /*SwitchOpcode*/ 25|128,1/*153*/, TARGET_VAL(ISD::FADD),// ->312490
156633 /*318915*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::FADD),// ->318937
157920 /*321265*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::FADD),// ->321286
164237 /*333279*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::FADD),// ->333553
169561 /*343982*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::FADD),// ->344252
174607 /*354302*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FADD),// ->354339
175935 /*356832*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FADD),// ->356869
180851 /*366339*/ /*SwitchOpcode*/ 52|128,2/*308*/, TARGET_VAL(ISD::FADD),// ->366651
185462 /*375137*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::FADD),// ->375159
186170 /*376416*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::FADD),// ->376437
233466 /*476090*/ /*SwitchOpcode*/ 59|128,1/*187*/, TARGET_VAL(ISD::FADD),// ->476281
234954 /*479218*/ /*SwitchOpcode*/ 43|128,1/*171*/, TARGET_VAL(ISD::FADD),// ->479393
236627 /*482711*/ OPC_SwitchOpcode /*8 cases */, 66|128,1/*194*/, TARGET_VAL(ISD::FADD),// ->482910
237649 /*484898*/ /*SwitchOpcode*/ 40|128,1/*168*/, TARGET_VAL(ISD::FADD),// ->485070
239898 /*489620*/ /*SwitchOpcode*/ 59|128,1/*187*/, TARGET_VAL(ISD::FADD),// ->489811
241386 /*492748*/ /*SwitchOpcode*/ 43|128,1/*171*/, TARGET_VAL(ISD::FADD),// ->492923
243144 /*496418*/ OPC_SwitchOpcode /*8 cases */, 66|128,1/*194*/, TARGET_VAL(ISD::FADD),// ->496617
244167 /*498607*/ /*SwitchOpcode*/ 40|128,1/*168*/, TARGET_VAL(ISD::FADD),// ->498779
gen/lib/Target/X86/X86GenFastISel.inc13513 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/BasicTTIImpl.h 407 if (TLI->isOperationLegalOrCustomOrPromote(ISD::FADD, VT))
include/llvm/CodeGen/TargetLowering.h 941 case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
2271 case ISD::FADD:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1562 case ISD::FADD: return visitFADD(N);
11865 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) {
11936 return DAG.getNode(ISD::FADD, DL, VT, N0, N1, Flags);
11940 return DAG.getNode(ISD::FADD, DL, VT, N1, N0, Flags);
11975 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B, Flags);
11981 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B, Flags);
12007 if (N1CFP && N0.getOpcode() == ISD::FADD &&
12009 SDValue NewC = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1, Flags);
12010 return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0), NewC, Flags);
12023 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1),
12029 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
12032 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1),
12044 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N1.getOperand(1),
12050 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
12053 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N1.getOperand(1),
12059 if (N0.getOpcode() == ISD::FADD) {
12069 if (N1.getOpcode() == ISD::FADD) {
12080 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
12080 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
12151 N1.getOpcode() == ISD::FADD) {
12163 ISD::FADD, DL, VT, N0,
12243 if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() &&
12253 return DAG.getNode(ISD::FADD, DL, VT, N0, N0, Flags);
12362 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
12364 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
12377 DAG.getNode(ISD::FADD, DL, VT, N1, N2.getOperand(1),
12398 return DAG.getNode(ISD::FADD, DL, VT, N0, N2);
12405 return DAG.getNode(ISD::FADD, DL, VT, N2, RHSNeg);
12422 DAG.getNode(ISD::FADD, DL, VT, N1,
12430 DAG.getNode(ISD::FADD, DL, VT, N1,
20311 Est = DAG.getNode(ISD::FADD, DL, VT, MulEst, NewEst, Flags);
20381 SDValue RHS = DAG.getNode(ISD::FADD, DL, VT, AEE, MinusThree, Flags);
lib/CodeGen/SelectionDAG/FastISel.cpp 1796 return selectBinaryOp(I, ISD::FADD);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2451 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
3175 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3179 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
4024 case ISD::FADD:
4346 case ISD::FADD:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 70 case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
1143 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break;
1608 Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
2074 case ISD::FADD:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 4045 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 370 case ISD::FADD:
1244 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1264 TLI.isOperationLegalOrCustom(ISD::FADD, VT))
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 110 case ISD::FADD:
934 case ISD::FADD:
2122 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break;
2755 case ISD::FADD:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3997 case ISD::FADD:
4989 case ISD::FADD:
5021 case ISD::FADD:
5119 case ISD::FADD:
7162 if (Opcode == ISD::FADD)
7754 case ISD::STRICT_FADD: NewOpc = ISD::FADD; break;
9036 case ISD::FADD:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 4924 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4927 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4940 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4943 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4946 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4961 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4964 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4967 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4970 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4973 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4976 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
5039 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5056 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5062 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5081 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5087 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5093 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5100 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
5135 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5152 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5158 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5178 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5184 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5190 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5197 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
5234 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
5253 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5274 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5280 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
5287 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
6158 SDValue Add = DAG.getNode(ISD::FADD, sdl,
8916 Res = DAG.getNode(ISD::FADD, dl, VT, Op1,
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 675 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 246 case ISD::FADD: return "fadd";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 2481 case ISD::FADD:
5389 case ISD::FADD:
5489 case ISD::FADD:
6051 !isOperationLegalOrCustom(ISD::FADD, DstVT) ||
6068 SDValue Slow = DAG.getNode(ISD::FADD, dl, DstVT, SignCvt, SignCvt);
6088 !isOperationLegalOrCustom(ISD::FADD, DstVT) ||
6112 Result = DAG.getNode(ISD::FADD, dl, DstVT, LoFlt, HiSub);
7321 case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break;
lib/CodeGen/TargetLoweringBase.cpp 1593 case FAdd: return ISD::FADD;
lib/Target/AArch64/AArch64ISelLowering.cpp 238 setOperationAction(ISD::FADD, MVT::f128, Custom);
401 setOperationAction(ISD::FADD, MVT::f16, Promote);
421 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
427 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
451 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
663 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
3008 case ISD::FADD:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 406 setOperationAction(ISD::FADD, VT, Expand);
500 setTargetDAGCombine(ISD::FADD);
516 case ISD::FADD:
2055 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2134 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2187 return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
2281 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2494 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
3656 case ISD::FADD: {
3674 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
3675 if (Res.getOpcode() != ISD::FADD)
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp 391 case ISD::FADD:
lib/Target/AMDGPU/R600ISelLowering.cpp 764 DAG.getNode(ISD::FADD, DL, VT,
780 DAG.getNode(ISD::FADD, DL, VT, FractPart,
lib/Target/AMDGPU/SIISelLowering.cpp 609 setOperationAction(ISD::FADD, MVT::v2f16, Legal);
636 setOperationAction(ISD::FADD, MVT::v4f16, Custom);
704 setTargetDAGCombine(ISD::FADD);
4077 case ISD::FADD:
8564 case ISD::FADD:
8733 case ISD::FADD:
9283 case ISD::FADD:
9621 if (LHS.getOpcode() == ISD::FADD) {
9633 if (RHS.getOpcode() == ISD::FADD) {
9664 if (LHS.getOpcode() == ISD::FADD) {
9678 if (RHS.getOpcode() == ISD::FADD) {
9947 case ISD::FADD:
lib/Target/ARM/ARMFastISel.cpp 1812 case ISD::FADD:
2851 return SelectBinaryFPOp(I, ISD::FADD);
lib/Target/ARM/ARMISelLowering.cpp 763 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
936 setOperationAction(ISD::FADD, MVT::f64, Expand);
11802 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
11805 Opcode != ISD::FADD && Opcode != ISD::FSUB)
lib/Target/Hexagon/HexagonISelLowering.cpp 1427 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1526 setOperationAction(ISD::FADD, MVT::f64, Expand);
1563 setOperationAction(ISD::FADD, MVT::f64, Legal);
lib/Target/Mips/MipsSEISelLowering.cpp 131 setOperationAction(ISD::FADD, MVT::f16, Promote);
387 setOperationAction(ISD::FADD, Ty, Legal);
1821 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
lib/Target/NVPTX/NVPTXISelLowering.cpp 519 setTargetDAGCombine(ISD::FADD);
536 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
2115 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, A, PointFiveWithSign);
2146 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, AbsA,
4390 if (User->getOpcode() != ISD::FADD)
4761 case ISD::FADD:
lib/Target/PowerPC/PPCISelLowering.cpp 883 setOperationAction(ISD::FADD, MVT::f128, Legal);
930 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
981 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
10075 case ISD::FADD:
lib/Target/Sparc/SparcISelLowering.cpp 1711 setOperationAction(ISD::FADD, MVT::f128, Legal);
1736 setOperationAction(ISD::FADD, MVT::f128, Custom);
3038 case ISD::FADD: return LowerF128Op(Op, DAG,
lib/Target/SystemZ/SystemZISelLowering.cpp 472 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
504 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
lib/Target/X86/X86ISelLowering.cpp 540 setOperationAction(ISD::FADD, VT, Custom);
671 setOperationAction(ISD::FADD, MVT::f128, Custom);
1852 setTargetDAGCombine(ISD::FADD);
8604 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
8779 if (Opcode != ISD::FADD && Opcode != ISD::FSUB)
8844 IsSubAdd = Opc[0] == ISD::FADD;
8973 case ISD::FADD: HOpcode = X86ISD::FHADD; break;
9011 if (GenericOpcode != ISD::ADD && GenericOpcode != ISD::FADD)
9155 else if (isHorizontalBinOpPart(BV, ISD::FADD, DAG, 0, NumElts, InVec0,
18598 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuffle, Sub);
18676 return DAG.getNode(ISD::FADD, DL, MVT::v2f64, fHI, fLO);
18767 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
18770 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
18892 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
19684 case ISD::FADD: HOpcode = X86ISD::FHADD; break;
19728 RTLIB::Libcall LC = Op.getOpcode() == ISD::FADD ? RTLIB::ADD_F128
27709 case ISD::FADD:
33591 if (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL || Opcode1 == ISD::FSUB ||
33596 (N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) {
33855 if ((V1.getOpcode() != ISD::FADD && V1.getOpcode() != ISD::FSUB) ||
33856 (V2.getOpcode() != ISD::FADD && V2.getOpcode() != ISD::FSUB) ||
33886 IsSubAdd = Op0Even ? V1->getOpcode() == ISD::FADD
33887 : V2->getOpcode() == ISD::FADD;
36226 case ISD::FADD: // Begin 2 operands
36275 DAG.matchBinOpReduction(ExtElt, Opc, {ISD::ADD, ISD::FADD}, true);
40918 bool IsFadd = N->getOpcode() == ISD::FADD;
44934 case ISD::FADD:
lib/Target/X86/X86IntrinsicsInfo.h 417 X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
418 X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
lib/Target/X86/X86TargetTransformInfo.cpp 207 { ISD::FADD, MVT::v2f64, 2 }, // addpd
542 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
546 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
694 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
695 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
751 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
752 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
753 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
754 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
836 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/
837 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/
851 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/
852 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/
2538 { ISD::FADD, MVT::v2f64, 2 },
2539 { ISD::FADD, MVT::v4f32, 4 },
2553 { ISD::FADD, MVT::v4f64, 5 },
2554 { ISD::FADD, MVT::v8f32, 7 },
2563 { ISD::FADD, MVT::v2f64, 2 },
2564 { ISD::FADD, MVT::v4f32, 4 },
2578 { ISD::FADD, MVT::v4f64, 3 },
2579 { ISD::FADD, MVT::v4f32, 3 },
2580 { ISD::FADD, MVT::v8f32, 4 },