reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenDAGISel.inc
114234 /*254363*/  /*SwitchOpcode*/ 44|128,2/*300*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->254667
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc
28537 /* 59808*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
28555 /* 59855*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
74682 /*165272*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
77084 /*171410*/  /*SwitchOpcode*/ 105|128,3/*489*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->171903
gen/lib/Target/Mips/MipsGenDAGISel.inc
11033 /* 20644*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11041 /* 20659*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11134 /* 20834*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11232 /* 21016*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11240 /* 21031*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11334 /* 21207*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11433 /* 21390*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11441 /* 21404*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11494 /* 21498*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11551 /* 21599*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11559 /* 21613*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11613 /* 21708*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11672 /* 21811*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11680 /* 21825*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11713 /* 21883*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11750 /* 21948*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11758 /* 21962*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11792 /* 22021*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11833 /* 22091*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11845 /* 22112*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11863 /* 22143*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11885 /* 22180*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11897 /* 22201*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11916 /* 22233*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11940 /* 22272*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11960 /* 22307*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
11980 /* 22340*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
12016 /* 22403*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
12484 /* 23274*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
12492 /* 23289*/            OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
12589 /* 23468*/            OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
12692 /* 23655*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
12700 /* 23670*/            OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
12794 /* 23846*/            OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
12897 /* 24037*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
12905 /* 24052*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13003 /* 24232*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13107 /* 24420*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13115 /* 24435*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13210 /* 24612*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13314 /* 24804*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13322 /* 24818*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13379 /* 24916*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13442 /* 25023*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13450 /* 25037*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13504 /* 25132*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13566 /* 25242*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13574 /* 25256*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13632 /* 25355*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13696 /* 25463*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13704 /* 25477*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13759 /* 25573*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13823 /* 25685*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13831 /* 25699*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13868 /* 25761*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13911 /* 25832*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13919 /* 25846*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13953 /* 25905*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
13995 /* 25979*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14003 /* 25993*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14041 /* 26056*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14085 /* 26128*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14093 /* 26142*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14128 /* 26202*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14173 /* 26280*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14185 /* 26301*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14211 /* 26343*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14246 /* 26399*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14258 /* 26420*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14277 /* 26452*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14303 /* 26497*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14315 /* 26518*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14342 /* 26561*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14378 /* 26618*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14390 /* 26639*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14410 /* 26672*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14438 /* 26718*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14471 /* 26772*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14495 /* 26814*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14529 /* 26869*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14554 /* 26910*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14604 /* 26987*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14625 /* 27023*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14648 /* 27058*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14673 /* 27097*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14693 /* 27132*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14716 /* 27167*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14741 /* 27206*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14761 /* 27241*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
14784 /* 27276*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18449 /* 34551*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18457 /* 34566*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18550 /* 34741*/          OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18648 /* 34923*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18656 /* 34938*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18750 /* 35114*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18849 /* 35297*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18857 /* 35311*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18910 /* 35405*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18967 /* 35506*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18975 /* 35520*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19029 /* 35615*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19088 /* 35718*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19096 /* 35732*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19129 /* 35790*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19166 /* 35855*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19174 /* 35869*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19208 /* 35928*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19249 /* 35998*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19261 /* 36019*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19279 /* 36050*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19301 /* 36087*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19313 /* 36108*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19332 /* 36140*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19356 /* 36179*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19376 /* 36214*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19396 /* 36247*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19432 /* 36310*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19673 /* 36761*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19765 /* 36935*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19859 /* 37110*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19911 /* 37203*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19965 /* 37298*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19997 /* 37355*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20033 /* 37418*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20050 /* 37448*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20238 /* 37799*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20330 /* 37973*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20424 /* 38148*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20476 /* 38241*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20530 /* 38336*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20562 /* 38393*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20598 /* 38456*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20615 /* 38486*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20792 /* 38817*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20884 /* 38991*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
20978 /* 39166*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
21030 /* 39259*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
21084 /* 39354*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
21116 /* 39411*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
21152 /* 39474*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
21169 /* 39504*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
27921 /* 52801*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
27930 /* 52817*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
27947 /* 52845*/        OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
28012 /* 52967*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
29011 /* 54879*/  /*SwitchOpcode*/ 33|128,1/*161*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->55044
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc
71427 /*150614*/  /*SwitchOpcode*/ 16, TARGET_VAL(ISD::BUILD_VECTOR),// ->150633
gen/lib/Target/PowerPC/PPCGenDAGISel.inc
39115 /* 98769*/  /*SwitchOpcode*/ 91|128,31/*4059*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->102832
gen/lib/Target/PowerPC/PPCGenFastISel.inc
 3234   case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Sparc/SparcGenDAGISel.inc
 3324 /*  6142*/  /*SwitchOpcode*/ 38, TARGET_VAL(ISD::BUILD_VECTOR),// ->6183
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc
17980 /* 34520*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18120 /* 34767*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
18260 /* 35014*/      OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
19208 /* 36676*/  /*SwitchOpcode*/ 21|128,5/*661*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->37341
gen/lib/Target/X86/X86GenDAGISel.inc
231218 /*471715*/  /*SwitchOpcode*/ 119|128,4/*631*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->472350
include/llvm/CodeGen/SelectionDAG.h
  752     return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
  761     return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
  779     return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
include/llvm/CodeGen/SelectionDAGNodes.h
 2006     return N->getOpcode() == ISD::BUILD_VECTOR;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  857   if (N.getOpcode() != ISD::BUILD_VECTOR)
  874   if (V.getOpcode() != ISD::BUILD_VECTOR)
 1592   case ISD::BUILD_VECTOR:       return visitBUILD_VECTOR(N);
 2848   if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
 8521          Cond.getOpcode() == ISD::BUILD_VECTOR);
10645   if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations &&
10663       N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
10967       N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
15156                                                : ISD::BUILD_VECTOR,
15189                                                : ISD::BUILD_VECTOR,
16642   if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
16651   if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
16833   if (IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR &&
16911     if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
17153       (!TLI.isOperationLegal(ISD::BUILD_VECTOR, VecVT) &&
17154        TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)))
17283   assert(BV->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector");
17916     return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
17928         if (ISD::BUILD_VECTOR == Op.getOpcode()) {
17943       if (ISD::BUILD_VECTOR == Op.getOpcode()) {
18290   if (V.getOpcode() == ISD::BUILD_VECTOR) {
18304               TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT))) &&
18530       if (S.getOpcode() == ISD::BUILD_VECTOR) {
18929     if (V->getOpcode() == ISD::BUILD_VECTOR) {
19458   if (RHS.getOpcode() != ISD::BUILD_VECTOR)
19564   if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() &&
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
 3652   case ISD::BUILD_VECTOR:
 4407   case ISD::BUILD_VECTOR: {
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
 1643   case ISD::BUILD_VECTOR:    Res = ExpandOp_BUILD_VECTOR(N); break;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
   99   case ISD::BUILD_VECTOR:
 1163   case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
 3604   case ISD::BUILD_VECTOR:      Res = ExpandOp_BUILD_VECTOR(N); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  909       TLI.getOperationAction(ISD::BUILD_VECTOR,  VT) == TargetLowering::Expand)
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
   51   case ISD::BUILD_VECTOR:      R = ScalarizeVecRes_BUILD_VECTOR(N); break;
  850   case ISD::BUILD_VECTOR:      SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
 2710   case ISD::BUILD_VECTOR:      Res = WidenVecRes_BUILD_VECTOR(N); break;
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  157   if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
  201   if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
  234   if (N->getOpcode() != ISD::BUILD_VECTOR)
  247   if (N->getOpcode() != ISD::BUILD_VECTOR)
  276   if (ISD::BUILD_VECTOR != Op.getOpcode())
  307   if (ISD::BUILD_VECTOR != LHS.getOpcode() ||
  308       ISD::BUILD_VECTOR != RHS.getOpcode())
  809   case ISD::BUILD_VECTOR: {
 2255   case ISD::BUILD_VECTOR: {
 2465   case ISD::BUILD_VECTOR:
 3386   if (Val.getOpcode() == ISD::BUILD_VECTOR)
 3440   case ISD::BUILD_VECTOR:
 4239     else if (Op.getOpcode() == ISD::BUILD_VECTOR)
 4464   case ISD::BUILD_VECTOR: {
 5064   case ISD::BUILD_VECTOR: {
 5256     if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
 5466   case ISD::BUILD_VECTOR: {
 7215   case ISD::BUILD_VECTOR:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  419                                                 : ISD::BUILD_VECTOR,
 5408   case ISD::BUILD_VECTOR:
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  155   case ISD::BUILD_VECTOR:               return "BUILD_VECTOR";
lib/CodeGen/SelectionDAG/TargetLowering.cpp
  823   case ISD::BUILD_VECTOR:
 2213   case ISD::BUILD_VECTOR: {
 5372   case ISD::BUILD_VECTOR: {
 5381         isOperationLegal(ISD::BUILD_VECTOR, VT))
 5476   case ISD::BUILD_VECTOR: {
lib/Target/AArch64/AArch64ISelLowering.cpp
  843   setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
 2652   if (N->getOpcode() != ISD::BUILD_VECTOR)
 2681   assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
 3032   case ISD::BUILD_VECTOR:
 6255   assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
 6951     if (V1.getOpcode() == ISD::BUILD_VECTOR &&
 7471   assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
10692   if (StVal.getOpcode() != ISD::BUILD_VECTOR)
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  105   assert(N->getOpcode() == ISD::BUILD_VECTOR && N->getNumOperands() == 2);
  491     case ISD::BUILD_VECTOR:
  771   case ISD::BUILD_VECTOR: {
  775       if (Opc == ISD::BUILD_VECTOR && NumVectorElts == 2) {
 2469   if (Src.getOpcode() == ISD::BUILD_VECTOR) {
 2778   case ISD::BUILD_VECTOR: {
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
 3038         isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) {
 3175     if (Vec.getOpcode() == ISD::BUILD_VECTOR) {
 3196         if (BV.getOpcode() == ISD::BUILD_VECTOR &&
 3888       if (Src.getOpcode() == ISD::BUILD_VECTOR) {
 3919         SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
 3930       SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
lib/Target/AMDGPU/R600ISelLowering.cpp
 1910     if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
 1922     if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
 1952     if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
 1959         Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
 2020     if (Arg.getOpcode() != ISD::BUILD_VECTOR)
 2038     if (Arg.getOpcode() != ISD::BUILD_VECTOR)
lib/Target/AMDGPU/SIISelLowering.cpp
  256       case ISD::BUILD_VECTOR:
  282     setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
  283     AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
  300   setOperationAction(ISD::BUILD_VECTOR, MVT::v4f16, Custom);
  301   setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
  514         case ISD::BUILD_VECTOR:
  576       setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
  577       setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
 4050   case ISD::BUILD_VECTOR:
 4741         = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture);
 8524       SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
 8811   case ISD::BUILD_VECTOR: {
 8927   if (N0.getOpcode() == ISD::BUILD_VECTOR && VT == MVT::v2f16 &&
lib/Target/ARM/ARMISelLowering.cpp
  176   setOperationAction(ISD::BUILD_VECTOR,      VT, Custom);
  252     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
  313     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
  314     setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
  357     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
  389     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
  922     setTargetDAGCombine(ISD::BUILD_VECTOR);
 7283     if (Lower.getOpcode() == ISD::BUILD_VECTOR)
 7287     if (Upper.getOpcode() == ISD::BUILD_VECTOR)
 7333   assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
 7831       if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
 8221         BVN->getOpcode() != ISD::BUILD_VECTOR)
 8242   if (N->getOpcode() != ISD::BUILD_VECTOR)
 8376     assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
 8384   assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
 8978     Build = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i1, Ops);
 9193   case ISD::BUILD_VECTOR:  return LowerBUILD_VECTOR(Op, DAG, Subtarget);
11046       || N0.getOpcode() != ISD::BUILD_VECTOR
11047       || N1.getOpcode() != ISD::BUILD_VECTOR)
14438   case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
lib/Target/Hexagon/HexagonISelLowering.cpp
 1436     ISD::BUILD_VECTOR,          ISD::SCALAR_TO_VECTOR,
 1479     setOperationAction(ISD::BUILD_VECTOR,       NativeVT, Custom);
 2849     case ISD::BUILD_VECTOR:         return LowerBUILD_VECTOR(Op, DAG);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
   94     setOperationAction(ISD::BUILD_VECTOR,       T, Custom);
  128     setOperationAction(ISD::BUILD_VECTOR,   T, Custom);
  186     setOperationAction(ISD::BUILD_VECTOR,       BoolV, Custom);
 1556     case ISD::BUILD_VECTOR:            return LowerHvxBuildVector(Op, DAG);
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
  965   case ISD::BUILD_VECTOR: {
lib/Target/Mips/MipsSEISelLowering.cpp
  329   setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
  383   setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
  465   case ISD::BUILD_VECTOR:       return lowerBUILD_VECTOR(Op, DAG);
lib/Target/NVPTX/NVPTXISelLowering.cpp
  387   setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
 2182   case ISD::BUILD_VECTOR:
 2378         SDValue V2 = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f16, E0, E1);
 4751   return DCI.DAG.getNode(ISD::BUILD_VECTOR, DL, CCType, CCNode.getValue(0),
lib/Target/PowerPC/PPCISelLowering.cpp
  648       setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
  736     setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
  737     setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
  738     setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
  739     setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
  859         setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
  860       setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
  954     setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
 1002     setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
 1043     setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
 1115   setTargetDAGCombine(ISD::BUILD_VECTOR);
 9557   Op = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, Op.getOperand(0),
10155   case ISD::BUILD_VECTOR:       return LowerBUILD_VECTOR(Op, DAG);
12628   assert(N->getOpcode() == ISD::BUILD_VECTOR &&
12713   assert(N->getOpcode() == ISD::BUILD_VECTOR &&
12932   assert(N->getOpcode() == ISD::BUILD_VECTOR &&
14082   case ISD::BUILD_VECTOR:
lib/Target/Sparc/SparcISelLowering.cpp
 1457     setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
 1585   case ISD::BUILD_VECTOR: {
lib/Target/SystemZ/SystemZISelLowering.cpp
  330       setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
 4766         Op0.getOpcode() == ISD::BUILD_VECTOR)
 4911           VSNOp0.getOpcode() == ISD::BUILD_VECTOR) {
 5018   case ISD::BUILD_VECTOR:
 5304     } else if (Opcode == ISD::BUILD_VECTOR &&
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  133       setOperationAction(ISD::BUILD_VECTOR, T, Custom);
  136         setOperationAction(ISD::BUILD_VECTOR, T, Custom);
 1010   case ISD::BUILD_VECTOR:
lib/Target/X86/X86ISelLowering.cpp
  818     setOperationAction(ISD::BUILD_VECTOR,       MVT::v4f32, Custom);
  909       setOperationAction(ISD::BUILD_VECTOR,       VT, Custom);
  916       setOperationAction(ISD::BUILD_VECTOR,       VT, Custom);
 1264       setOperationAction(ISD::BUILD_VECTOR,       VT, Custom);
 1300     setOperationAction(ISD::BUILD_VECTOR,       MVT::v1i1, Custom);
 1341       setOperationAction(ISD::BUILD_VECTOR,     VT, Custom);
 1501       setOperationAction(ISD::BUILD_VECTOR,        VT, Custom);
 1609       setOperationAction(ISD::BUILD_VECTOR,       VT, Custom);
 1668       setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
 5475   if (Vec.getOpcode() == ISD::BUILD_VECTOR)
 7403   if (V.getOpcode() == ISD::BUILD_VECTOR)
10461     if (V.getOpcode() != ISD::BUILD_VECTOR)
12237   if (V.getOpcode() == ISD::BUILD_VECTOR ||
12392       V0Opc != ISD::BUILD_VECTOR)
12582       ((V.getOpcode() == ISD::BUILD_VECTOR && V.hasOneUse()) ||
25679       Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
27674   case ISD::BUILD_VECTOR:       return LowerBUILD_VECTOR(Op, DAG);
35584     if (N0.getOpcode() == ISD::BUILD_VECTOR &&
35605     if (N0.getOpcode() == ISD::BUILD_VECTOR &&
41279   if (N00.getOpcode() != ISD::BUILD_VECTOR ||
41280       N01.getOpcode() != ISD::BUILD_VECTOR ||
41281       N10.getOpcode() != ISD::BUILD_VECTOR ||
41282       N11.getOpcode() != ISD::BUILD_VECTOR)
42847     if (LHS.getOpcode() == ISD::BUILD_VECTOR) {
43846   if (Op0.getOpcode() != ISD::BUILD_VECTOR ||
43847       Op1.getOpcode() != ISD::BUILD_VECTOR)
43981   if (N00.getOpcode() != ISD::BUILD_VECTOR ||
43982       N01.getOpcode() != ISD::BUILD_VECTOR ||
43983       N10.getOpcode() != ISD::BUILD_VECTOR ||
43984       N11.getOpcode() != ISD::BUILD_VECTOR)
44637   if (InVec.getOpcode() == ISD::BUILD_VECTOR)