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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc94541 /*214677*/ OPC_CheckOpcode, TARGET_VAL(ISD::BSWAP),
94654 /*214906*/ /*SwitchOpcode*/ 62, TARGET_VAL(ISD::BSWAP),// ->214971
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4273 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc63362 /*138307*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::BSWAP),// ->138359
gen/lib/Target/ARM/ARMGenDAGISel.inc21660 /* 46510*/ OPC_CheckOpcode, TARGET_VAL(ISD::BSWAP),
21807 /* 46857*/ OPC_CheckOpcode, TARGET_VAL(ISD::BSWAP),
32808 /* 72217*/ OPC_CheckOpcode, TARGET_VAL(ISD::BSWAP),
32835 /* 72277*/ OPC_CheckOpcode, TARGET_VAL(ISD::BSWAP),
32936 /* 72498*/ OPC_CheckOpcode, TARGET_VAL(ISD::BSWAP),
32963 /* 72558*/ OPC_CheckOpcode, TARGET_VAL(ISD::BSWAP),
38510 /* 84903*/ /*SwitchOpcode*/ 113, TARGET_VAL(ISD::BSWAP),// ->85019
gen/lib/Target/ARM/ARMGenFastISel.inc 2708 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AVR/AVRGenDAGISel.inc 1377 /* 2394*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::BSWAP),// ->2407
gen/lib/Target/BPF/BPFGenDAGISel.inc 1063 /* 1798*/ OPC_CheckOpcode, TARGET_VAL(ISD::BSWAP),
1787 /* 3106*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::BSWAP),// ->3134
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc67405 /*129607*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::BSWAP),// ->129877
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 2265 /* 4687*/ /*SwitchOpcode*/ 36, TARGET_VAL(ISD::BSWAP),// ->4726
4648 /* 9259*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::BSWAP),// ->9272
gen/lib/Target/Mips/MipsGenDAGISel.inc26357 /* 49887*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::BSWAP),// ->49957
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc21410 /* 40229*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::BSWAP),// ->40253
gen/lib/Target/X86/X86GenDAGISel.inc 6200 /* 13302*/ OPC_CheckOpcode, TARGET_VAL(ISD::BSWAP),
37728 /* 78960*/ /*SwitchOpcode*/ 121, TARGET_VAL(ISD::BSWAP),// ->79084
gen/lib/Target/X86/X86GenFastISel.inc 5907 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2143 /* 3742*/ /*SwitchOpcode*/ 8, TARGET_VAL(ISD::BSWAP),// ->3753
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1539 case ISD::BSWAP: return visitBSWAP(N);
4329 if (HandOpcode == ISD::BSWAP) {
5333 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5427 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
5533 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) {
5557 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5587 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT,
6386 case ISD::BSWAP:
6588 if (NeedsBswap && LegalOperations && !TLI.isOperationLegal(ISD::BSWAP, VT))
6607 CombinedValue = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, CombinedValue);
6753 if (NeedsBswap && LegalOperations && !TLI.isOperationLegal(ISD::BSWAP, VT))
6771 return NeedsBswap ? DAG.getNode(ISD::BSWAP, SDLoc(N), VT, NewLoad) : NewLoad;
8033 return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N0);
8035 if (N0.getOpcode() == ISD::BSWAP)
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2558 Tmp = (Sz > 8 ? DAG.getNode(ISD::BSWAP, dl, VT, Op) : Op);
2681 case ISD::BSWAP:
4167 case ISD::BSWAP: {
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 60 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
389 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
1690 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
2453 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
2454 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 386 case ISD::BSWAP:
780 case ISD::BSWAP:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 74 case ISD::BSWAP:
886 case ISD::BSWAP:
2887 case ISD::BSWAP:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3217 case ISD::BSWAP: {
4326 case ISD::BSWAP:
4444 case ISD::BSWAP:
4608 case ISD::BSWAP:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6198 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 385 case ISD::BSWAP: return "bswap";
lib/Target/AArch64/AArch64ISelLowering.cpp 769 setOperationAction(ISD::BSWAP, VT, Expand);
9884 if (N0.getOpcode() == ISD::BSWAP) {
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 321 setOperationAction(ISD::BSWAP, VT, Expand);
390 setOperationAction(ISD::BSWAP, VT, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 352 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
452 setOperationAction(ISD::BSWAP, MVT::i16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 267 setOperationAction(ISD::BSWAP, VT, Legal);
722 setOperationAction(ISD::BSWAP, VT, Expand);
1091 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
13752 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
lib/Target/AVR/AVRISelLowering.cpp 113 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
lib/Target/BPF/BPFISelLowering.cpp 107 setOperationAction(ISD::BSWAP, MVT::i32, Promote);
lib/Target/Hexagon/HexagonISelLowering.cpp 1365 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
1366 setOperationAction(ISD::BSWAP, MVT::i64, Legal);
1980 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
2007 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 86 setOperationAction(ISD::BSWAP, T, Legal);
lib/Target/Lanai/LanaiISelLowering.cpp 125 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
lib/Target/MSP430/MSP430ISelLowering.cpp 967 Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
972 Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
lib/Target/Mips/Mips16ISelLowering.cpp 146 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
147 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
lib/Target/Mips/MipsISelLowering.cpp 487 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
489 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
lib/Target/NVPTX/NVPTXISelLowering.cpp 432 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
433 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
434 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
lib/Target/PowerPC/PPCISelLowering.cpp 326 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
328 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
330 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
657 setOperationAction(ISD::BSWAP, VT, Expand);
1123 setTargetDAGCombine(ISD::BSWAP);
10179 case ISD::BSWAP:
13435 if (cast<StoreSDNode>(N)->isUnindexed() && Opcode == ISD::BSWAP &&
13881 case ISD::BSWAP:
lib/Target/RISCV/RISCVISelLowering.cpp 138 setOperationAction(ISD::BSWAP, XLenVT, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1569 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1635 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 616 setTargetDAGCombine(ISD::BSWAP);
5607 Op1.getOpcode() == ISD::BSWAP &&
5701 if (Op.getOpcode() == ISD::BSWAP && Op.hasOneUse()) {
5707 Op = DAG.getNode(ISD::BSWAP, SDLoc(N), EltVT, Op);
5893 Vec.getOpcode() == ISD::BSWAP || Vec.isUndef() ||
5895 Elt.getOpcode() == ISD::BSWAP || Elt.isUndef() ||
5908 Vec = DAG.getNode(ISD::BSWAP, SDLoc(N), VecVT, Vec);
5910 Elt = DAG.getNode(ISD::BSWAP, SDLoc(N), EltVT, Elt);
5924 Op0.getOpcode() == ISD::BSWAP || Op0.isUndef() ||
5926 Op1.getOpcode() == ISD::BSWAP || Op1.isUndef()) {
5936 Op0 = DAG.getNode(ISD::BSWAP, SDLoc(N), VecVT, Op0);
5938 Op1 = DAG.getNode(ISD::BSWAP, SDLoc(N), VecVT, Op1);
6170 case ISD::BSWAP: return combineBSWAP(N, DCI);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 112 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
lib/Target/X86/X86ISelLowering.cpp 410 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
772 setOperationAction(ISD::BSWAP, VT, Expand);
lib/Target/X86/X86TargetTransformInfo.cpp 1963 { ISD::BSWAP, MVT::v4i64, 1 },
1964 { ISD::BSWAP, MVT::v8i32, 1 },
1965 { ISD::BSWAP, MVT::v16i16, 1 },
2000 { ISD::BSWAP, MVT::v4i64, 4 },
2001 { ISD::BSWAP, MVT::v8i32, 4 },
2002 { ISD::BSWAP, MVT::v16i16, 4 },
2055 { ISD::BSWAP, MVT::v2i64, 1 },
2056 { ISD::BSWAP, MVT::v4i32, 1 },
2057 { ISD::BSWAP, MVT::v8i16, 1 },
2076 { ISD::BSWAP, MVT::v2i64, 7 },
2077 { ISD::BSWAP, MVT::v4i32, 7 },
2078 { ISD::BSWAP, MVT::v8i16, 7 },
2156 ISD = ISD::BSWAP;