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reference to multiple definitions → definitions
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References
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc29118 /* 56199*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
gen/lib/Target/Mips/MipsGenDAGISel.inc21426 /* 39970*/ OPC_SwitchOpcode /*2 cases */, 19, TARGET_VAL(ISD::AssertZext),// ->39993
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 96 /* 87*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
124 /* 137*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
156 /* 197*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
218 /* 315*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
246 /* 365*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
278 /* 425*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
397 /* 657*/ /*SwitchOpcode*/ 91|128,3/*475*/, TARGET_VAL(ISD::AssertZext),// ->1136
434 /* 733*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
463 /* 785*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
496 /* 847*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
560 /* 969*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
589 /* 1021*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
622 /* 1083*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
5486 /* 10138*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
12751 /* 23759*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 4766 /* 8630*/ OPC_SwitchOpcode /*9 cases */, 32|128,3/*416*/, TARGET_VAL(ISD::AssertZext),// ->9051
5910 /* 10819*/ OPC_SwitchOpcode /*8 cases */, 32|128,3/*416*/, TARGET_VAL(ISD::AssertZext),// ->11240
gen/lib/Target/X86/X86GenDAGISel.inc254000 N->getOpcode() != ISD::AssertZext;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1121 case ISD::AssertZext:
1123 return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1));
1555 case ISD::AssertZext: return visitAssertExt(N);
4813 case ISD::AssertZext: {
4816 EVT VT = Op.getOpcode() == ISD::AssertZext ?
10141 Opcode == ISD::AssertZext) {
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 764 Result = DAG.getNode(ISD::AssertZext, dl,
2776 LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 57 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
219 return DAG.getNode(ISD::AssertZext, SDLoc(N),
528 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
1688 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
2431 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
2435 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 615 Promoted = DAG.getNode(Op->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3021 case ISD::AssertZext: {
3436 case ISD::AssertZext:
5174 case ISD::AssertZext: {
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 873 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
5402 case ISD::AssertZext:
8599 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op,
9330 AssertOp = ISD::AssertZext;
9827 AssertOp = ISD::AssertZext;
9867 if (Res.getOpcode() == ISD::AssertZext)
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 108 case ISD::AssertZext: return "AssertZext";
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 2781 case ISD::AssertZext:
lib/CodeGen/SelectionDAG/TargetLowering.cpp 1786 case ISD::AssertZext: {
3459 if (Op0.getOpcode() == ISD::AssertZext &&
lib/Target/AArch64/AArch64ISelLowering.cpp 3304 ArgValue = DAG.getNode(ISD::AssertZext, DL, ArgValue.getValueType(),
5521 FrameAddr = DAG.getNode(ISD::AssertZext, DL, MVT::i64, FrameAddr,
11165 case ISD::AssertZext: {
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 504 setTargetDAGCombine(ISD::AssertZext);
4073 case ISD::AssertZext:
lib/Target/AMDGPU/SIISelLowering.cpp 1443 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
2150 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
2181 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2200 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2402 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
5131 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
8266 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE,
10238 if (Op.getOpcode() == ISD::AssertZext)
lib/Target/ARM/ARMISelLowering.cpp 4094 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
14403 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
14406 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
14409 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
lib/Target/AVR/AVRISelLowering.cpp 1103 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
lib/Target/BPF/BPFISelLowering.cpp 250 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 1512 case ISD::AssertZext:
lib/Target/Lanai/LanaiISelLowering.cpp 474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
lib/Target/MSP430/MSP430ISelLowering.cpp 649 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
lib/Target/Mips/MipsISelLowering.cpp 507 setTargetDAGCombine(ISD::AssertZext);
3386 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3448 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 1390 case ISD::AssertZext: {
2762 (Input.getOperand(0).getOpcode() == ISD::AssertZext ||
lib/Target/PowerPC/PPCISelLowering.cpp 3684 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
5200 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
lib/Target/Sparc/SparcISelLowering.cpp 617 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
1333 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
lib/Target/SystemZ/SystemZISelLowering.cpp 1249 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
lib/Target/X86/X86ISelLowering.cpp 3282 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4222 if (TruncInput.getOpcode() == ISD::AssertZext &&
28136 Res = DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext