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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenDAGISel.inc21437 /* 39993*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::AssertSext),// ->40013
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 5341 /* 9896*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertSext),
5346 /* 9904*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertSext),
5386 /* 9975*/ OPC_SwitchOpcode /*2 cases */, 19, TARGET_VAL(ISD::AssertSext),// ->9998
5415 /* 10023*/ /*SwitchOpcode*/ 29, TARGET_VAL(ISD::AssertSext),// ->10055
5794 /* 10679*/ OPC_SwitchOpcode /*2 cases */, 45, TARGET_VAL(ISD::AssertSext),// ->10728
5799 /* 10688*/ OPC_SwitchOpcode /*2 cases */, 16, TARGET_VAL(ISD::AssertSext),// ->10708
5828 /* 10738*/ OPC_SwitchOpcode /*2 cases */, 14, TARGET_VAL(ISD::AssertSext),// ->10756
7656 /* 14385*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::AssertSext),// ->14405
gen/lib/Target/X86/X86GenDAGISel.inc253999 N->getOpcode() != ISD::AssertSext &&
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1117 case ISD::AssertSext:
1119 return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1));
1554 case ISD::AssertSext:
10140 N0.getOperand(0).getOpcode() == ISD::AssertSext &&
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2769 LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res,
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 56 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
212 return DAG.getNode(ISD::AssertSext, SDLoc(N),
528 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
1687 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
2409 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
2413 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 616 : ISD::AssertSext,
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3433 case ISD::AssertSext:
5173 case ISD::AssertSext:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 873 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
5403 case ISD::AssertSext:
9328 AssertOp = ISD::AssertSext;
9825 AssertOp = ISD::AssertSext;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 107 case ISD::AssertSext: return "AssertSext";
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 2780 case ISD::AssertSext:
lib/Target/AArch64/AArch64ISelLowering.cpp11156 case ISD::AssertSext: {
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 505 setTargetDAGCombine(ISD::AssertSext);
4074 case ISD::AssertSext:
lib/Target/AMDGPU/SIISelLowering.cpp 1443 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
2195 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val,
2407 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
lib/Target/ARM/ARMISelLowering.cpp 4089 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
lib/Target/AVR/AVRISelLowering.cpp 1098 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
lib/Target/BPF/BPFISelLowering.cpp 247 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 1511 case ISD::AssertSext:
lib/Target/Hexagon/HexagonISelLowering.cpp 840 if (Op.getOpcode() != ISD::AssertSext)
lib/Target/Lanai/LanaiISelLowering.cpp 471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
lib/Target/MSP430/MSP430ISelLowering.cpp 646 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
lib/Target/Mips/MipsISelLowering.cpp 3392 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3443 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 2727 (Input.getOperand(0).getOpcode() == ISD::AssertSext ||
lib/Target/PowerPC/PPCISelLowering.cpp 3681 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
5205 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
15148 ExtsSrc.getOperand(0).getOpcode() == ISD::AssertSext)
lib/Target/Sparc/SparcISelLowering.cpp 454 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
613 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
1329 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
lib/Target/SystemZ/SystemZISelLowering.cpp 1246 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
lib/Target/X86/X86ISelLowering.cpp 3279 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
28137 : ISD::AssertSext,