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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc98689 /*222401*/ /*SwitchOpcode*/ 26|128,4/*538*/, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->222943
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc49319 /*106070*/ /*SwitchOpcode*/ 25|128,3/*409*/, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->106483
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 7465 /* 28717*/ /*SwitchOpcode*/ 113, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->28833
gen/lib/Target/AVR/AVRGenDAGISel.inc 1195 /* 2066*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->2103
gen/lib/Target/Mips/MipsGenDAGISel.inc23808 /* 44674*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->44744
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc56950 /*121454*/ /*SwitchOpcode*/ 111|128,3/*495*/, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->121953
gen/lib/Target/PowerPC/PPCGenDAGISel.inc22171 /* 55016*/ /*SwitchOpcode*/ 79, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->55098
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 8973 /* 16668*/ /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->17145
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc19699 /* 36851*/ /*SwitchOpcode*/ 103|128,2/*359*/, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->37214
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 335 /* 491*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
369 /* 551*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
403 /* 610*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
437 /* 670*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
1011 /* 1693*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
1044 /* 1756*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
1577 /* 2752*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
1608 /* 2812*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
2167 /* 3834*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
2196 /* 3886*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
2225 /* 3937*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
2254 /* 3989*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
2857 /* 5066*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
2883 /* 5114*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
3283 /* 5870*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
3311 /* 5925*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
3879 /* 7003*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
3905 /* 7055*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
4297 /* 7816*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
4318 /* 7856*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
5349 /* 9746*/ /*SwitchOpcode*/ 88|128,1/*216*/, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->9966
6498 /* 11970*/ /*SwitchOpcode*/ 105|128,2/*361*/, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->12335
13648 /* 26456*/ /*SwitchOpcode*/ 89|128,4/*601*/, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->27061
include/llvm/CodeGen/SelectionDAGNodes.h 1412 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1469 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3782 case ISD::ATOMIC_LOAD_AND:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 168 case ISD::ATOMIC_LOAD_AND:
1718 case ISD::ATOMIC_LOAD_AND:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 594 case ISD::ATOMIC_LOAD_AND:
6519 Opcode == ISD::ATOMIC_LOAD_AND ||
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 4595 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 89 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd";
lib/CodeGen/TargetLoweringBase.cpp 462 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
lib/Target/AArch64/AArch64ISelLowering.cpp 510 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
3085 case ISD::ATOMIC_LOAD_AND:
lib/Target/AMDGPU/SIISelLowering.cpp 739 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
9979 case ISD::ATOMIC_LOAD_AND:
lib/Target/ARM/ARMISelLowering.cpp 1231 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
lib/Target/Mips/Mips16ISelLowering.cpp 135 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 224 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
4990 case ISD::ATOMIC_LOAD_AND:
lib/Target/X86/X86ISelLowering.cpp 472 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom);
27119 case ISD::ATOMIC_LOAD_AND:
27671 case ISD::ATOMIC_LOAD_AND: return lowerAtomicArith(Op, DAG, Subtarget);
28424 case ISD::ATOMIC_LOAD_AND: