reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenDAGISel.inc

96607 /*218595*/  /*SwitchOpcode*/ 58|128,2/*314*/, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->218913

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

48113 /*103592*/  /*SwitchOpcode*/ 25|128,3/*409*/, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->104005

gen/lib/Target/AMDGPU/R600GenDAGISel.inc

 6798 /* 26746*/  /*SwitchOpcode*/ 125|128,1/*253*/, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->27003

gen/lib/Target/AVR/AVRGenDAGISel.inc

 1153 /*  1992*/  /*SwitchOpcode*/ 34, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->2029

gen/lib/Target/BPF/BPFGenDAGISel.inc

  484 /*   846*/  /*SwitchOpcode*/ 65, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->914

gen/lib/Target/Mips/MipsGenDAGISel.inc

23728 /* 44534*/  /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->44604

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

55228 /*118460*/  /*SwitchOpcode*/ 111|128,3/*495*/, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->118959

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

22091 /* 54852*/  /*SwitchOpcode*/ 79, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->54934

gen/lib/Target/RISCV/RISCVGenDAGISel.inc

 8698 /* 16191*/  /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->16668

gen/lib/Target/SystemZ/SystemZGenDAGISel.inc

19593 /* 36634*/  /*SwitchOpcode*/ 85|128,1/*213*/, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->36851

gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc

   63 /*    15*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
   97 /*    75*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
  131 /*   134*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
  165 /*   194*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
  879 /*  1443*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
  912 /*  1506*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 1453 /*  2514*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 1484 /*  2574*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 1935 /*  3422*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 1964 /*  3474*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 1993 /*  3525*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 2022 /*  3577*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 2753 /*  4876*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 2779 /*  4924*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 3171 /*  5652*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 3199 /*  5707*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 3775 /*  6797*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 3801 /*  6849*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 4213 /*  7658*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 4234 /*  7698*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
 5119 /*  9306*/      /*SwitchOpcode*/ 88|128,1/*216*/, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->9526
 6128 /* 11240*/      /*SwitchOpcode*/ 105|128,2/*361*/, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->11605
13088 /* 25246*/  /*SwitchOpcode*/ 89|128,4/*601*/, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->25851

gen/lib/Target/X86/X86GenDAGISel.inc

53878 /*114160*/  /*SwitchOpcode*/ 90, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->114253

include/llvm/CodeGen/SelectionDAGNodes.h

 1410            N->getOpcode() == ISD::ATOMIC_LOAD_ADD     ||
 1467            N->getOpcode() == ISD::ATOMIC_LOAD_ADD     ||

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 3780   case ISD::ATOMIC_LOAD_ADD:

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

  166   case ISD::ATOMIC_LOAD_ADD:
 1716   case ISD::ATOMIC_LOAD_ADD:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  592   case ISD::ATOMIC_LOAD_ADD:
 6517   assert((Opcode == ISD::ATOMIC_LOAD_ADD ||

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 4593   case AtomicRMWInst::Add:  NT = ISD::ATOMIC_LOAD_ADD; break;

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

   87   case ISD::ATOMIC_LOAD_ADD:            return "AtomicLoadAdd";

lib/CodeGen/TargetLoweringBase.cpp

  460     OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)

lib/Target/AArch64/AArch64ISelLowering.cpp

 8262   return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, AN->getMemoryVT(),

lib/Target/AMDGPU/SIISelLowering.cpp

  737   setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
 9977   case ISD::ATOMIC_LOAD_ADD:

lib/Target/ARM/ARMISelLowering.cpp

 1229     setOperationAction(ISD::ATOMIC_LOAD_ADD,  MVT::i32, Expand);

lib/Target/Mips/Mips16ISelLowering.cpp

  133   setOperationAction(ISD::ATOMIC_LOAD_ADD,    MVT::i32,   Expand);

lib/Target/SystemZ/SystemZISelLowering.cpp

  222   setOperationAction(ISD::ATOMIC_LOAD_ADD,  MVT::i32, Custom);
 3764       return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
 4986   case ISD::ATOMIC_LOAD_ADD:

lib/Target/X86/X86ISelLowering.cpp

  469     setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom);
27107   case ISD::ATOMIC_LOAD_ADD:
27153       return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, VT, Chain, LHS,
27156     assert(Opc == ISD::ATOMIC_LOAD_ADD &&
27667   case ISD::ATOMIC_LOAD_ADD:
28422   case ISD::ATOMIC_LOAD_ADD:
37280   if (Opc != ISD::ATOMIC_LOAD_ADD && Opc != ISD::ATOMIC_LOAD_SUB)