reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenDAGISel.inc

98236 /*221457*/  /*SwitchOpcode*/ 79|128,2/*335*/, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->221796

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

57469 /*125694*/  /*SwitchOpcode*/ 41|128,1/*169*/, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->125867

gen/lib/Target/AMDGPU/R600GenDAGISel.inc

 7582 /* 29065*/  /*SwitchOpcode*/ 16|128,1/*144*/, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->29213

gen/lib/Target/Mips/MipsGenDAGISel.inc

24008 /* 45024*/  /*SwitchOpcode*/ 72, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->45099

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

53346 /*115049*/  /*SwitchOpcode*/ 89|128,10/*1369*/, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->116422

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

22491 /* 55672*/  /*SwitchOpcode*/ 84, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->55759

gen/lib/Target/RISCV/RISCVGenDAGISel.inc

11203 /* 20634*/  /*SwitchOpcode*/ 15|128,5/*655*/, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->21293

gen/lib/Target/Sparc/SparcGenDAGISel.inc

 2846 /*  5269*/  /*SwitchOpcode*/ 59, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->5331

gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc

 2631 /*  4658*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
 2661 /*  4712*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
 2691 /*  4765*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
 2721 /*  4819*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
 3507 /*  6306*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
 3536 /*  6363*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
 4087 /*  7415*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
 4114 /*  7469*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
 4465 /*  8132*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
 4487 /*  8174*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
 4768 /*  8636*/        OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
 4984 /*  9051*/      /*SwitchOpcode*/ 123|128,1/*251*/, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->9306
 5912 /* 10825*/        OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
14768 /* 28876*/  /*SwitchOpcode*/ 114|128,4/*626*/, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->29506

include/llvm/CodeGen/SelectionDAGNodes.h

 1407            N->getOpcode() == ISD::ATOMIC_CMP_SWAP     ||
 1451     return Op == ISD::ATOMIC_CMP_SWAP ||
 1464     return N->getOpcode() == ISD::ATOMIC_CMP_SWAP     ||

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 2734         ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
 2757         ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
 3791   case ISD::ATOMIC_CMP_SWAP: {

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

  180   case ISD::ATOMIC_CMP_SWAP:
 1728   case ISD::ATOMIC_CMP_SWAP: {
 1738         ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  589   case ISD::ATOMIC_CMP_SWAP:
 6506   assert(Opcode == ISD::ATOMIC_CMP_SWAP ||

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

   84   case ISD::ATOMIC_CMP_SWAP:            return "AtomicCmpSwap";

lib/CodeGen/TargetLoweringBase.cpp

  459     OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

 2884   case ISD::ATOMIC_CMP_SWAP:

lib/Target/AArch64/AArch64ISelLowering.cpp

  507   setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
12093   case ISD::ATOMIC_CMP_SWAP:

lib/Target/AMDGPU/SIISelLowering.cpp

  339   setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
  340   setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
  734   setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
 4031   case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
 9974   case ISD::ATOMIC_CMP_SWAP:

lib/Target/ARM/ARMISelDAGToDAG.cpp

 4282   case ISD::ATOMIC_CMP_SWAP:

lib/Target/ARM/ARMISelLowering.cpp

 1207       setOperationAction(ISD::ATOMIC_CMP_SWAP,  MVT::i64, Custom);
 1227     setOperationAction(ISD::ATOMIC_CMP_SWAP,  MVT::i32, Expand);
 9316   case ISD::ATOMIC_CMP_SWAP:

lib/Target/AVR/AVRISelLowering.cpp

  135     setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand);

lib/Target/Mips/Mips16ISelLowering.cpp

  131   setOperationAction(ISD::ATOMIC_CMP_SWAP,    MVT::i32,   Expand);

lib/Target/PowerPC/PPCISelLowering.cpp

  161   setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
 9574   assert(Op.getOpcode() == ISD::ATOMIC_CMP_SWAP &&
10181   case ISD::ATOMIC_CMP_SWAP:

lib/Target/Sparc/SparcISelLowering.cpp

 1597     setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);