reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

10410   if ((N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
18613           TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT))
18615                               DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG,
18639   if (Opcode != ISD::ANY_EXTEND_VECTOR_INREG &&

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

  108   case ISD::ANY_EXTEND_VECTOR_INREG:
 4238       case ISD::ANY_EXTEND_VECTOR_INREG:

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

  432   case ISD::ANY_EXTEND_VECTOR_INREG:
  774   case ISD::ANY_EXTEND_VECTOR_INREG:
 1008   Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src);

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

   66   case ISD::ANY_EXTEND_VECTOR_INREG:
  424   case ISD::ANY_EXTEND_VECTOR_INREG:
  878   case ISD::ANY_EXTEND_VECTOR_INREG:
 2030     case ISD::ANY_EXTEND_VECTOR_INREG:
 2827   case ISD::ANY_EXTEND_VECTOR_INREG:
 3285         return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
 3395       case ISD::ANY_EXTEND_VECTOR_INREG:
 3409     case ISD::ANY_EXTEND_VECTOR_INREG:
 4264     return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, InOp);

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 4592   case ISD::ANY_EXTEND_VECTOR_INREG:

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  316   case ISD::ANY_EXTEND_VECTOR_INREG:    return "any_extend_vector_inreg";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 1638           IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
 1671           IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
 1702   case ISD::ANY_EXTEND_VECTOR_INREG: {
 1707     bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG;
 2446   case ISD::ANY_EXTEND_VECTOR_INREG:
 2459     if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG &&

lib/CodeGen/TargetLoweringBase.cpp

  690       setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);

lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

  105       setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom);
  138     setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG,  T, Custom);
 1429   assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG);
 1573     case ISD::ANY_EXTEND_VECTOR_INREG: return LowerHvxExtend(Op, DAG);

lib/Target/SystemZ/SystemZISelLowering.cpp

 5333                 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&

lib/Target/X86/X86ISelDAGToDAG.cpp

  852     case ISD::ANY_EXTEND_VECTOR_INREG: {

lib/Target/X86/X86ISelLowering.cpp

 1868   setTargetDAGCombine(ISD::ANY_EXTEND_VECTOR_INREG);
 5826   case ISD::ANY_EXTEND_VECTOR_INREG:
 5827     return ISD::ANY_EXTEND_VECTOR_INREG;
 7202   case ISD::ANY_EXTEND_VECTOR_INREG: {
 7213         (ISD::ANY_EXTEND == Opcode || ISD::ANY_EXTEND_VECTOR_INREG == Opcode);
44724          InOpcode == ISD::ANY_EXTEND_VECTOR_INREG ||
44959   case ISD::ANY_EXTEND_VECTOR_INREG: