reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

60211 /*131761*/  /*SwitchOpcode*/ 30, TARGET_VAL(ISD::ADDE),// ->131794

gen/lib/Target/AVR/AVRGenDAGISel.inc

 1035 /*  1776*/  /*SwitchOpcode*/ 69, TARGET_VAL(ISD::ADDE),// ->1848

gen/lib/Target/Lanai/LanaiGenDAGISel.inc

  768 /*  1354*/  /*SwitchOpcode*/ 73, TARGET_VAL(ISD::ADDE),// ->1430

gen/lib/Target/MSP430/MSP430GenDAGISel.inc

  975 /*  1997*/      /*SwitchOpcode*/ 27|128,3/*411*/, TARGET_VAL(ISD::ADDE),// ->2412
 3650 /*  7387*/  /*SwitchOpcode*/ 73|128,1/*201*/, TARGET_VAL(ISD::ADDE),// ->7592

gen/lib/Target/Mips/MipsGenDAGISel.inc

26347 /* 49869*/  /*SwitchOpcode*/ 15, TARGET_VAL(ISD::ADDE),// ->49887

gen/lib/Target/Mips/MipsGenFastISel.inc

 3408   case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

57908 /*123130*/  /*SwitchOpcode*/ 34, TARGET_VAL(ISD::ADDE),// ->123167

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

24368 /* 59035*/  /*SwitchOpcode*/ 89, TARGET_VAL(ISD::ADDE),// ->59127

gen/lib/Target/PowerPC/PPCGenFastISel.inc

 3232   case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);

gen/lib/Target/Sparc/SparcGenDAGISel.inc

 2235 /*  4113*/  /*SwitchOpcode*/ 36, TARGET_VAL(ISD::ADDE),// ->4152

include/llvm/CodeGen/TargetLowering.h

 2279     case ISD::ADDE:

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1505   case ISD::ADDE:               return visitADDE(N);
 2667     return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
10790   if ((N0.getOpcode() == ISD::ADDE || N0.getOpcode() == ISD::ADDCARRY) &&

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

  146   case ISD::ADDE:
 1769   case ISD::ADDE:
 2169       Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
 2266     Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 3066   case ISD::ADDE: {
 3071     if (Opcode == ISD::ADDE)

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  286   case ISD::ADDE:                       return "adde";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 5729                   isOperationLegalOrCustom(ISD::ADDE, VT));
 5745     Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero,

lib/CodeGen/TargetLoweringBase.cpp

  673     setOperationAction(ISD::ADDE, VT, Expand);

lib/Target/AArch64/AArch64ISelLowering.cpp

  299   setOperationAction(ISD::ADDE, MVT::i32, Custom);
  303   setOperationAction(ISD::ADDE, MVT::i64, Custom);
 2332   case ISD::ADDE:
 2997   case ISD::ADDE:

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  740   case ISD::ADDE:
  985   bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE);
  988   bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE;

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  328     setOperationAction(ISD::ADDE, VT, Legal);

lib/Target/AMDGPU/R600ISelLowering.cpp

  260     setOperationAction(ISD::ADDE, VT, Expand);

lib/Target/AVR/AVRISelLowering.cpp

   70     setOperationAction(ISD::ADDE, VT, Legal);

lib/Target/Lanai/LanaiAluCode.h

  122   case ISD::ADDE:

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

  219   assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!");
  762   case ISD::ADDE: {

lib/Target/Mips/MipsSEISelLowering.cpp

  109       setOperationAction(ISD::ADDE, MVT::i32, Legal);

lib/Target/PowerPC/PPCISelLowering.cpp

  193     setOperationAction(ISD::ADDE, VT, Legal);
15240     return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),
15255     return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),

lib/Target/Sparc/SparcISelLowering.cpp

 1549   setOperationAction(ISD::ADDE, MVT::i32, Custom);
 1555     setOperationAction(ISD::ADDE, MVT::i64, Custom);
 2904   case ISD::ADDC: hiOpc = ISD::ADDE; break;
 2905   case ISD::ADDE: hasChain = true; break;
 3053   case ISD::ADDE:

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  114         ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {