reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
262 if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) { 280 for (MachineInstr &UseInst : MRI.use_nodbg_instructions(DefReg)) { 308 for (MachineInstr &DbgVal : MRI.use_instructions(DefReg)) { 345 if (Reg && !MRI.use_empty(Reg)) 470 LastLocalValue = MRI.getVRegDef(Reg); 2017 return MRI.createVirtualRegister(RC); 2025 if (!MRI.constrainRegClass(Op, RegClass)) { 2232 const TargetRegisterClass *RC = MRI.getRegClass(Op0); 2233 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); 2356 if (!MRI.hasOneUse(LoadReg)) 2359 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg);lib/Target/AArch64/AArch64FastISel.cpp
2047 auto *MI = MRI.getUniqueVRegDef(Reg); 2079 MI = MRI.getUniqueVRegDef(Reg); 2778 MRI.clearKillFlags(UseReg); 3480 Register SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); 3894 if (!MRI.getRegClass(SrcReg)->contains(DestReg)) 4020 Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); 4173 Register TmpReg = MRI.createVirtualRegister(RC); 4294 Register TmpReg = MRI.createVirtualRegister(RC); 4403 Register TmpReg = MRI.createVirtualRegister(RC); 4462 Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); 4535 MachineInstr *MI = MRI.getUniqueVRegDef(Reg); 4546 LoadMI = MRI.getUniqueVRegDef(LoadReg); 4617 MRI.clearKillFlags(UseReg);lib/Target/ARM/ARMFastISel.cpp
2158 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
lib/Target/Mips/MipsFastISel.cpp 1733 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
lib/Target/PowerPC/PPCFastISel.cpp416 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); 469 (ResultReg ? MRI.getRegClass(ResultReg) : 613 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; 629 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); 867 auto RC1 = MRI.getRegClass(SrcReg1); 868 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr; 990 auto RC = MRI.getRegClass(SrcReg); 1177 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; 1217 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg); 1227 auto RC = MRI.getRegClass(SrcReg); 1282 (AssignedReg ? MRI.getRegClass(AssignedReg) : 1315 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); 1319 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); 1332 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); 1341 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); 1923 (AssignedReg ? MRI.getRegClass(AssignedReg) : 2420 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); 2422 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);lib/Target/WebAssembly/WebAssemblyFastISel.cpp
580 assert(MRI.getRegClass(Reg) == &WebAssembly::I32RegClass); 590 unsigned ResultReg = createResultReg(MRI.getRegClass(Reg)); 720 MRI.addLiveIn(WebAssembly::ARGUMENTS);lib/Target/X86/X86FastISel.cpp
1247 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); 1761 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) { 2107 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { 2325 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {