|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenCallingConv.inc 95 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
225 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
239 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
264 if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
277 if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
290 if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
303 if (unsigned Reg = State.AllocateReg(RegList17, RegList18)) {
322 if (unsigned Reg = State.AllocateReg(RegList19, RegList20)) {
469 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
483 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
508 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
521 if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
534 if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
547 if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
566 if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
1064 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
1077 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
1090 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
1103 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
1116 if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
1135 if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
1207 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
1220 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
1233 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
1246 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
gen/lib/Target/ARM/ARMGenCallingConv.inc 145 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
696 if (unsigned Reg = State.AllocateReg(RegList2, RegList3)) {
869 if (unsigned Reg = State.AllocateReg(RegList2, RegList3)) {
gen/lib/Target/BPF/BPFGenCallingConv.inc 34 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
47 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
gen/lib/Target/Mips/MipsGenCallingConv.inc 158 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
171 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
184 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
252 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
gen/lib/Target/X86/X86GenCallingConv.inc 2223 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
2236 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
2249 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
2264 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
2279 if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
2299 if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
lib/Target/ARM/ARMCallingConv.cpp 72 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList);
122 unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
lib/Target/PowerPC/PPCCallingConv.cpp 147 unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
lib/Target/RISCV/RISCVISelLowering.cpp 1576 Reg = State.AllocateReg(ArgFPR32s, ArgFPR64s);
1578 Reg = State.AllocateReg(ArgFPR64s, ArgFPR32s);