reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenGICombiner.inc

   76   return DisabledRules.test(RuleID);

include/llvm/ADT/SparseBitVector.h

  532     bool old = test(Idx);

include/llvm/CodeGen/LiveVariables.h

  300   bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); }

include/llvm/DebugInfo/PDB/Native/HashTable.h

   72     assert(Map->Present.test(Index));
   84       if (Map->Present.test(Index))
  265   bool isPresent(uint32_t K) const { return Present.test(K); }
  266   bool isDeleted(uint32_t K) const { return Deleted.test(K); }

lib/Analysis/BlockFrequencyInfoImpl.cpp

  588   return IsIrrLoopHeader.test(Node.Index);

lib/CodeGen/LiveVariables.cpp

  108   if (VRInfo.AliveBlocks.test(BBNum))
  173   if (!VRInfo.AliveBlocks.test(BBNum))
  726   if (AliveBlocks.test(Num))
  750     if (VI.AliveBlocks.test(SuccIdx))
  805     if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))

lib/CodeGen/MachineVerifier.cpp

 2322         if (!VI.AliveBlocks.test(MBB.getNumber())) {
 2328         if (VI.AliveBlocks.test(MBB.getNumber())) {

lib/DebugInfo/PDB/Native/HashTable.cpp

   62       if (Vec.test(Idx))

lib/Target/X86/X86SpeculativeLoadHardening.cpp

 1676               return Op.isReg() && LoadDepRegs.test(Op.getReg());
 1734         if ((BaseReg && LoadDepRegs.test(BaseReg)) ||
 1735             (IndexReg && LoadDepRegs.test(IndexReg)))

unittests/ADT/SparseBitVectorTest.cpp

   19   EXPECT_FALSE(Vec.test(17));
   21   EXPECT_TRUE(Vec.test(5));
   22   EXPECT_FALSE(Vec.test(17));
   24   EXPECT_TRUE(Vec.test(5));
   25   EXPECT_FALSE(Vec.test(6));
   27   EXPECT_FALSE(Vec.test(5));
   30   EXPECT_TRUE(Vec.test(17));
   32   EXPECT_FALSE(Vec.test(17));
   36   EXPECT_TRUE(ConstVec.test(5));
   37   EXPECT_FALSE(ConstVec.test(17));
   40   EXPECT_TRUE(Vec.test(1337));
   42   EXPECT_FALSE(Vec.test(1337));
   48   EXPECT_TRUE(MovedVec.test(5));
   49   EXPECT_TRUE(MovedVec.test(1337));
   62   EXPECT_TRUE(Vec.test(1));
   92   EXPECT_TRUE(Vec.test(23));
   93   EXPECT_TRUE(Vec.test(234));
   99   EXPECT_TRUE(Vec.test(17));
  100   EXPECT_TRUE(Vec.test(256));
  106   EXPECT_TRUE(Vec.test(56));
  107   EXPECT_TRUE(Vec.test(517));
  128   EXPECT_TRUE(Vec.test(42));
  129   EXPECT_FALSE(Vec.test(567));
  138   EXPECT_FALSE(Vec.test(19));
  139   EXPECT_TRUE(Vec.test(31));

utils/TableGen/CodeGenRegisters.cpp

  250   return RegUnits.test(Unit);