reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/ADT/APSInt.h

  142     return IsUnsigned ? APSInt(lshr(Amt), true) : APSInt(ashr(Amt), false);

lib/Analysis/BasicAliasAnalysis.cpp

  438   return (Offset << ShiftBits).ashr(ShiftBits);

lib/Analysis/ConstantFolding.cpp

 2321                            Rhs.sextOrSelf(ExtendedWidth)).ashr(Scale);

lib/Analysis/ScalarEvolution.cpp

 5568           APInt::getSignedMaxValue(BitWidth).ashr(TZ).shl(TZ) + 1);
 5723             ConstantRange(APInt::getSignedMinValue(BitWidth).ashr(NS - 1),
 5724                           APInt::getSignedMaxValue(BitWidth).ashr(NS - 1) + 1),

lib/Analysis/ValueTracking.cpp

 1211       return KnownZero.ashr(ShiftAmt);
 1215       return KnownOne.ashr(ShiftAmt);
 5467         Upper = C->ashr(ShiftAmount) + 1;
 5470         Lower = C->ashr(ShiftAmount);

lib/CodeGen/GlobalISel/GISelKnownBits.cpp

  328       Known.Zero = Known.Zero.ashr(Shift);
  329       Known.One = Known.One.ashr(Shift);

lib/ExecutionEngine/Interpreter/Execution.cpp

 1257       Result.IntVal = valueToShift.ashr(getShiftAmount(shiftAmount, valueToShift));
 1264     Dest.IntVal = valueToShift.ashr(getShiftAmount(shiftAmount, valueToShift));
 2095     Dest.IntVal = Op0.IntVal.ashr(Op1.IntVal.getZExtValue());

lib/Target/AArch64/AArch64ISelLowering.cpp

 9416   APInt ShiftedConstValue = ConstValue.ashr(TrailingZeroes);

lib/Target/AArch64/AArch64TargetTransformInfo.cpp

   75     APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

 1451       .addImm(Imm.ashr(32).getZExtValue());

lib/Target/Hexagon/HexagonConstPropagation.cpp

 1775     Result = A1.shl(BW-Bits-Offset).ashr(BW-Bits);

lib/Target/RISCV/Utils/RISCVMatInt.cpp

   85     APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);

lib/Target/X86/X86ISelLowering.cpp

22501         Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));

lib/Target/X86/X86TargetTransformInfo.cpp

 2952     APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);

lib/Transforms/InstCombine/InstCombineCompares.cpp

 1192     if (IsAShr && AP1 == AP2.ashr(Shift)) {
 2201       if (ShiftedC.ashr(ShAmtVal) == C)
 2208           (ShiftedC + 1).ashr(ShAmtVal) == (C + 1))
 2235   assert(((IsAShr && C.shl(ShAmtVal).ashr(ShAmtVal) == C) ||

lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

  929                       (BitMask1.ashr(ShrAmt) << ShlAmt);
  935                         BitMask2.ashr(ShrAmt - ShlAmt);

tools/lldb/source/Utility/Scalar.cpp

 2747     m_integer = m_integer.ashr(bit_offset)

unittests/ADT/APIntTest.cpp

   37   EXPECT_EQ(neg_one, neg_one.ashr(7));
  291   EXPECT_EQ(one, one.ashr(1));
 2402   EXPECT_TRUE(signmin32.ashr(32).isAllOnesValue());
 2406   EXPECT_EQ(0, umax32.ashr(32));
 2410   EXPECT_TRUE(signmin128.ashr(128).isAllOnesValue());
 2414   EXPECT_EQ(0, umax128.ashr(128));