reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/X86/X86GenDAGISel.inc

18480 /* 37288*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20048 /* 40440*/            OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20466 /* 41432*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20498 /* 41495*/      OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20734 /* 42057*/      OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20739 /* 42075*/      OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20754 /* 42116*/      OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20769 /* 42156*/      OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20795 /* 42208*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20802 /* 42233*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20812 /* 42254*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20819 /* 42279*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
20882 /* 42406*/          OPC_EmitInteger, MVT::i32, X86::sub_32bit,
39988 /* 83745*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
39994 /* 83767*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
50881 /*107449*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
50894 /*107484*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
50907 /*107519*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
50930 /*107583*/          OPC_EmitInteger, MVT::i32, X86::sub_32bit,
50971 /*107685*/      OPC_EmitInteger, MVT::i32, X86::sub_32bit,
50986 /*107724*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
50998 /*107757*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
51010 /*107790*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55055 /*116687*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55274 /*117165*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55402 /*117437*/          OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55422 /*117482*/            OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55442 /*117526*/            OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55459 /*117557*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55475 /*117594*/          OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55492 /*117632*/          OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55504 /*117660*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55751 /*118167*/          OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55945 /*118539*/          OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55955 /*118564*/          OPC_EmitInteger, MVT::i32, X86::sub_32bit,
55965 /*118589*/          OPC_EmitInteger, MVT::i32, X86::sub_32bit,
57582 /*121746*/        OPC_EmitInteger, MVT::i32, X86::sub_32bit,
58732 /*123801*/      OPC_EmitInteger, MVT::i32, X86::sub_32bit,

gen/lib/Target/X86/X86GenFastISel.inc

 2019   return fastEmitInst_extractsubreg(MVT::i32, Op0, Op0IsKill, X86::sub_32bit);

lib/Target/X86/X86CallFrameOptimization.cpp

  548             .addImm(X86::sub_32bit);

lib/Target/X86/X86FastISel.cpp

 1557       .addImm(0).addReg(Result32).addImm(X86::sub_32bit);
 1969             .addImm(0).addReg(Zero32).addImm(X86::sub_32bit);
 3706         .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);

lib/Target/X86/X86FixupLEAs.cpp

  378       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
  380       IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
  553       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
  555       IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);

lib/Target/X86/X86FlagsCopyLowering.cpp

  927                        X86::NoSubRegister, X86::sub_32bit};

lib/Target/X86/X86ISelDAGToDAG.cpp

 2410     Base = CurDAG->getTargetInsertSubreg(X86::sub_32bit, DL, MVT::i64, ImplDef,
 2422     Index = CurDAG->getTargetInsertSubreg(X86::sub_32bit, DL, MVT::i64, ImplDef,
 4897                           CurDAG->getTargetConstant(X86::sub_32bit, dl,
 5082         SubRegOp = X86::sub_32bit;

lib/Target/X86/X86ISelLowering.cpp

29419         .addImm(X86::sub_32bit);
31055         .addImm(X86::sub_32bit);

lib/Target/X86/X86InstrInfo.cpp

  129       SubIdx = X86::sub_32bit;
  746             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
 4213     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
 4594     Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
 4930         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
 4932         NewMI->getOperand(0).setSubReg(X86::sub_32bit);

lib/Target/X86/X86InstructionSelector.cpp

  205     SubIdx = X86::sub_32bit;
  746     SubIdx = X86::sub_32bit;
  839           .addImm(X86::sub_32bit);
 1672             .addImm(X86::sub_32bit);

lib/Target/X86/X86RegisterInfo.cpp

  227       SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)

lib/Target/X86/X86SpeculativeLoadHardening.cpp

  493         .addImm(X86::sub_32bit);
 2293     unsigned SubRegImms[] = {X86::sub_8bit, X86::sub_16bit, X86::sub_32bit};