|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/X86/X86GenAsmMatcher.inc 7174 case X86::RSP: OpKind = MCK_Reg76; break;
gen/lib/Target/X86/X86GenInstrInfo.inc16568 static const MCPhysReg ImplicitList6[] = { X86::RSP, X86::SSP, 0 };
16581 static const MCPhysReg ImplicitList19[] = { X86::RSP, X86::EFLAGS, X86::SSP, 0 };
16612 static const MCPhysReg ImplicitList50[] = { X86::RBP, X86::RSP, 0 };
16636 static const MCPhysReg ImplicitList74[] = { X86::RSP, 0 };
16639 static const MCPhysReg ImplicitList77[] = { X86::RSP, X86::EFLAGS, X86::DF, 0 };
16659 static const MCPhysReg ImplicitList97[] = { X86::RAX, X86::RSP, X86::EFLAGS, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 1963 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
1993 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
2013 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2023 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
2033 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
2043 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
2063 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP,
2073 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2083 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
2123 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
2143 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP,
2173 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
2193 X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
2213 X86::RAX, X86::RCX, X86::RDX, X86::RSP,
2253 X86::RBP, X86::RSP,
2353 X86::RSP,
2719 { 7U, X86::RSP },
2886 { 7U, X86::RSP },
3063 { X86::RSP, 7U },
3213 { X86::RSP, -2U },
3363 { X86::RSP, -2U },
3513 { X86::RSP, 7U },
3663 { X86::RSP, -2U },
3813 { X86::RSP, -2U },
10040 static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10042 static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
10044 static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, 0 };
10052 static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10054 static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
10068 static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10070 static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
lib/Target/X86/AsmParser/X86AsmParser.cpp 1029 IndexReg == X86::ESP || IndexReg == X86::RSP) {
1915 if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
1916 (IndexReg == X86::ESP || IndexReg == X86::RSP))
lib/Target/X86/Disassembler/X86Disassembler.cpp 270 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
507 ALL_REGS
552 ALL_SIB_BASES
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp 576 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 163 {codeview::RegisterId::RSP, X86::RSP},
355 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
616 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
644 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
681 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
717 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
753 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
754 return X86::RSP;
lib/Target/X86/X86FixupLEAs.cpp 372 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP))
lib/Target/X86/X86FrameLowering.cpp 187 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
635 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
639 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
652 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
722 X86::RSP, false, RCXShadowSlot);
726 X86::RSP, false, RDXShadowSlot);
732 BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
733 .addReg(X86::RSP)
798 unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP;
1646 TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true);
2376 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2378 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2672 SPReg = X86::RSP;
lib/Target/X86/X86ISelDAGToDAG.cpp 395 (RegNode->getReg() == X86::RSP))
lib/Target/X86/X86ISelLowering.cpp24258 .Case("rsp", X86::RSP)
26639 DAG.getRegister(X86::RSP, MVT::i64), // Base
30058 IsLP64 || Subtarget.isTargetNaCl64() ? X86::RSP : X86::ESP;
lib/Target/X86/X86InstrInfo.cpp 8080 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
8080 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
8081 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
8082 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
lib/Target/X86/X86RegisterInfo.cpp 64 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
527 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
lib/Target/X86/X86RetpolineThunks.cpp 232 const unsigned SPReg = Is64Bit ? X86::RSP : X86::ESP;
lib/Target/X86/X86SpeculativeLoadHardening.cpp 1917 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), X86::RSP)
1918 .addReg(X86::RSP)
1935 .addReg(X86::RSP);
1964 } else if (BaseMO.getReg() == X86::RSP) {
2521 .addReg(/*Base*/ X86::RSP)
tools/llvm-exegesis/lib/X86/Target.cpp 388 .addReg(X86::RSP)
389 .addReg(X86::RSP)
398 .addReg(X86::RSP) // BaseReg
412 .addReg(X86::RSP) // BaseReg
422 .addReg(X86::RSP)
423 .addReg(X86::RSP)
471 .addReg(X86::RSP) // BaseReg
487 .addReg(X86::RSP) // BaseReg
unittests/tools/llvm-exegesis/X86/TargetTest.cpp 84 ElementsAre(IsReg(X86::RSP), IsImm(1), IsReg(0), IsImm(Offset),
90 ElementsAre(IsReg(Reg), IsReg(X86::RSP), IsImm(1), IsReg(0),
96 ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size)));
96 ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size)));
101 ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size)));
101 ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size)));