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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenAsmMatcher.inc 7172 case X86::RDI: OpKind = MCK_Reg71; break;
gen/lib/Target/X86/X86GenCallingConv.inc 210 X86::RDI, X86::RSI, X86::RDX, X86::RCX
1457 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1670 X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1741 X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14
1910 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1931 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
2373 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2394 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3371 X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14, X86::R15
3651 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3672 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3851 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3872 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
gen/lib/Target/X86/X86GenDAGISel.inc18642 /* 37553*/ OPC_EmitCopyToReg, 3, X86::RDI,
18650 /* 37567*/ OPC_EmitCopyToReg, 3, X86::RDI,
18711 /* 37666*/ OPC_EmitCopyToReg, 3, X86::RDI,
gen/lib/Target/X86/X86GenGlobalISel.inc10154 GIR_AddRegister, /*InsnID*/1, X86::RDI, /*AddRegisterRegFlags*/RegState::Define,
10200 GIR_AddRegister, /*InsnID*/1, X86::RDI, /*AddRegisterRegFlags*/RegState::Define,
gen/lib/Target/X86/X86GenInstrInfo.inc16618 static const MCPhysReg ImplicitList56[] = { X86::RDI, 0 };
16643 static const MCPhysReg ImplicitList81[] = { X86::RCX, X86::RDI, X86::RSI, 0 };
16646 static const MCPhysReg ImplicitList84[] = { X86::AL, X86::RCX, X86::RDI, 0 };
16647 static const MCPhysReg ImplicitList85[] = { X86::RCX, X86::RDI, 0 };
16649 static const MCPhysReg ImplicitList87[] = { X86::RAX, X86::RCX, X86::RDI, 0 };
16651 static const MCPhysReg ImplicitList89[] = { X86::AX, X86::RCX, X86::RDI, 0 };
16660 static const MCPhysReg ImplicitList98[] = { X86::RAX, X86::RDI, X86::DF, 0 };
16664 static const MCPhysReg ImplicitList102[] = { X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, X86::DF, 0 };
16666 static const MCPhysReg ImplicitList104[] = { X86::RBX, X86::RDX, X86::RSI, X86::RDI, 0 };
16667 static const MCPhysReg ImplicitList105[] = { X86::RSI, X86::RDI, 0 };
16671 static const MCPhysReg ImplicitList109[] = { X86::RAX, X86::RSI, X86::RDI, 0 };
16672 static const MCPhysReg ImplicitList110[] = { X86::RDX, X86::RDI, 0 };
16673 static const MCPhysReg ImplicitList111[] = { X86::RAX, X86::RDI, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 1963 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
1993 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
2003 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
2013 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2023 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
2043 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
2053 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11,
2083 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
2113 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
2123 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
2173 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
2183 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI,
2293 X86::RDI, X86::RBP,
2303 X86::RSI, X86::RDI,
2383 X86::RDI,
2717 { 5U, X86::RDI },
2884 { 5U, X86::RDI },
3059 { X86::RDI, 5U },
3209 { X86::RDI, -2U },
3359 { X86::RDI, -2U },
3509 { X86::RDI, 5U },
3659 { X86::RDI, -2U },
3809 { X86::RDI, -2U },
10018 static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
10020 static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
10022 static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
10024 static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
10036 static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RDI, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
10038 static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10040 static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10042 static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
10044 static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, 0 };
10060 static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
10062 static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
10064 static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
10066 static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
10072 static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
lib/Target/X86/AsmParser/X86AsmParser.cpp 1228 unsigned Basereg = is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
1242 case X86::RDI:
1254 return IsSIReg ? X86::RSI : X86::RDI;
lib/Target/X86/AsmParser/X86Operand.h 397 (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
lib/Target/X86/Disassembler/X86Disassembler.cpp 270 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
360 baseRegNo = insn.hasAdSize ? X86::EDI : X86::RDI;
507 ALL_REGS
552 ALL_SIB_BASES
568 EA_BASES_64BIT
645 ALL_EA_BASES
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp 1306 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 161 {codeview::RegisterId::RDI, X86::RDI},
612 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
640 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
677 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
713 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
749 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
750 return X86::RDI;
lib/Target/X86/X86FastISel.cpp 3121 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
lib/Target/X86/X86ISelLowering.cpp 3129 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
30092 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
30097 .addReg(X86::RDI, RegState::Implicit)
30246 BuildMI(*BB, MI, DL, TII->get(X86::MOV64rm), X86::RDI)
30254 addDirectMem(MIB, X86::RDI);
46066 case X86::RDI:
lib/Target/X86/X86MCInstLower.cpp 920 .addReg(X86::RDI)
1340 const Register DestRegs[] = {X86::RDI, X86::RSI};
1435 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
lib/Target/X86/X86SelectionDAGInfo.cpp 56 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
158 Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RDI : X86::EDI,
191 const unsigned DI = Use64BitRegs ? X86::RDI : X86::EDI;
302 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI,
tools/llvm-exegesis/lib/X86/Target.cpp 604 return TT.isOSWindows() ? X86::RCX : X86::RDI;
unittests/tools/llvm-exegesis/X86/SnippetFileTest.cpp 85 ASSERT_THAT(Snippet.LiveIns, ElementsAre(X86::RDI, X86::DL));
unittests/tools/llvm-exegesis/X86/TargetTest.cpp 361 State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
363 EXPECT_THAT(IT.getValueFor(I.Operands[2]), IsReg(X86::RDI));
374 State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
376 EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(X86::RDI));