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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenGlobalISel.inc 858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
1634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
1635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
1653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
2672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
2673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
2691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
4064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
4065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
4083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
4105 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
4138 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
4426 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
4524 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
4839 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
4937 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
5743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
5744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
5773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
5795 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
5828 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
5966 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
6043 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
6189 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
6266 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID,
7134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
8062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR8RegClassID,
10268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
10301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
10764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
10995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
11017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
11431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
11504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
11716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
11717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
11850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
11927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
11980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
11981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
12111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
12187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
12240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
12241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
12371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
12447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
gen/lib/Target/X86/X86GenInstrInfo.inc16715 static const MCOperandInfo OperandInfo42[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
16715 static const MCOperandInfo OperandInfo42[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
16716 static const MCOperandInfo OperandInfo43[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16716 static const MCOperandInfo OperandInfo43[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16716 static const MCOperandInfo OperandInfo43[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16739 static const MCOperandInfo OperandInfo66[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16756 static const MCOperandInfo OperandInfo83[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16757 static const MCOperandInfo OperandInfo84[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
16757 static const MCOperandInfo OperandInfo84[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
16819 static const MCOperandInfo OperandInfo146[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
16819 static const MCOperandInfo OperandInfo146[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
16819 static const MCOperandInfo OperandInfo146[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
16834 static const MCOperandInfo OperandInfo161[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
16835 static const MCOperandInfo OperandInfo162[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
16836 static const MCOperandInfo OperandInfo163[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16836 static const MCOperandInfo OperandInfo163[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16847 static const MCOperandInfo OperandInfo174[] = { { X86::GR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16848 static const MCOperandInfo OperandInfo175[] = { { X86::GR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16863 static const MCOperandInfo OperandInfo190[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
16863 static const MCOperandInfo OperandInfo190[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
16966 static const MCOperandInfo OperandInfo293[] = { { X86::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16969 static const MCOperandInfo OperandInfo296[] = { { X86::GR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16972 static const MCOperandInfo OperandInfo299[] = { { X86::GR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16982 static const MCOperandInfo OperandInfo309[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, X86::OPERAND_COND_CODE, 0 }, };
17079 static const MCOperandInfo OperandInfo406[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
17685 static const MCOperandInfo OperandInfo1012[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
17685 static const MCOperandInfo OperandInfo1012[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
17685 static const MCOperandInfo OperandInfo1012[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
17685 static const MCOperandInfo OperandInfo1012[] = { { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
gen/lib/Target/X86/X86GenRegisterBank.inc 38 (1u << (X86::GR8RegClassID - 0)) |
gen/lib/Target/X86/X86GenRegisterInfo.inc 2590 { GR8, GR8Bits, 213, 20, sizeof(GR8Bits), X86::GR8RegClassID, 1, true },
6256 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
6284 &X86MCRegisterClasses[GR8RegClassID],
lib/Target/X86/X86RegisterInfo.cpp 159 case X86::GR8RegClassID: