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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenDAGISel.inc57422 /*121471*/ OPC_EmitInteger, MVT::i32, X86::FR64XRegClassID,
59037 /*124428*/ OPC_EmitInteger, MVT::i32, X86::FR64XRegClassID,
59066 /*124514*/ OPC_EmitInteger, MVT::i32, X86::FR64XRegClassID,
59105 /*124612*/ OPC_EmitInteger, MVT::i32, X86::FR64XRegClassID,
59140 /*124718*/ OPC_EmitInteger, MVT::i32, X86::FR64XRegClassID,
gen/lib/Target/X86/X86GenGlobalISel.inc 7100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID,
7112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID,
12777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID,
12778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID,
12779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID,
13080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID,
13081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID,
13082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID,
13383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID,
13384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID,
13385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID,
13686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID,
13687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID,
13688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID,
13984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID,
14131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID,
14266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID,
14334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID,
14377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID,
14401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID,
14585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID,
14604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID,
14843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID,
14862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID,
16893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID,
16894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID,
gen/lib/Target/X86/X86GenInstrInfo.inc16723 static const MCOperandInfo OperandInfo50[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
16816 static const MCOperandInfo OperandInfo143[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
16816 static const MCOperandInfo OperandInfo143[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
16816 static const MCOperandInfo OperandInfo143[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
17038 static const MCOperandInfo OperandInfo365[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
17038 static const MCOperandInfo OperandInfo365[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
17040 static const MCOperandInfo OperandInfo367[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17040 static const MCOperandInfo OperandInfo367[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17040 static const MCOperandInfo OperandInfo367[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17136 static const MCOperandInfo OperandInfo463[] = { { X86::VK1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
17139 static const MCOperandInfo OperandInfo466[] = { { X86::VK1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
17139 static const MCOperandInfo OperandInfo466[] = { { X86::VK1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
17146 static const MCOperandInfo OperandInfo473[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
17147 static const MCOperandInfo OperandInfo474[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17147 static const MCOperandInfo OperandInfo474[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17236 static const MCOperandInfo OperandInfo563[] = { { X86::FR32XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR32XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17238 static const MCOperandInfo OperandInfo565[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17238 static const MCOperandInfo OperandInfo565[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17245 static const MCOperandInfo OperandInfo572[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17245 static const MCOperandInfo OperandInfo572[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17252 static const MCOperandInfo OperandInfo579[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR32XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17252 static const MCOperandInfo OperandInfo579[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR32XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17254 static const MCOperandInfo OperandInfo581[] = { { X86::GR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17255 static const MCOperandInfo OperandInfo582[] = { { X86::GR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17306 static const MCOperandInfo OperandInfo633[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
17306 static const MCOperandInfo OperandInfo633[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
17306 static const MCOperandInfo OperandInfo633[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
17307 static const MCOperandInfo OperandInfo634[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17307 static const MCOperandInfo OperandInfo634[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17307 static const MCOperandInfo OperandInfo634[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17307 static const MCOperandInfo OperandInfo634[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17308 static const MCOperandInfo OperandInfo635[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, X86::OPERAND_ROUNDING_CONTROL, 0 }, };
17308 static const MCOperandInfo OperandInfo635[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, X86::OPERAND_ROUNDING_CONTROL, 0 }, };
17308 static const MCOperandInfo OperandInfo635[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, X86::OPERAND_ROUNDING_CONTROL, 0 }, };
17308 static const MCOperandInfo OperandInfo635[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, X86::OPERAND_ROUNDING_CONTROL, 0 }, };
17438 static const MCOperandInfo OperandInfo765[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::GR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17469 static const MCOperandInfo OperandInfo796[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
17680 static const MCOperandInfo OperandInfo1007[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
17680 static const MCOperandInfo OperandInfo1007[] = { { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { X86::FR64XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { X86::SEGMENT_REGRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
gen/lib/Target/X86/X86GenRegisterBank.inc 124 (1u << (X86::FR64XRegClassID - 64)) |
gen/lib/Target/X86/X86GenRegisterInfo.inc 2654 { FR64X, FR64XBits, 1229, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 1, true },
7052 &X86MCRegisterClasses[FR64XRegClassID],
lib/Target/X86/X86RegisterInfo.cpp 153 case X86::FR64XRegClassID: