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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenAsmMatcher.inc 7192 case X86::FP0: OpKind = MCK_RFP32; break;
gen/lib/Target/X86/X86GenCallingConv.inc 890 if (unsigned Reg = State.AllocateReg(X86::FP0)) {
1962 if (unsigned Reg = State.AllocateReg(X86::FP0)) {
2425 if (unsigned Reg = State.AllocateReg(X86::FP0)) {
2833 X86::FP0, X86::FP1
2904 X86::FP0, X86::FP1
3114 X86::FP0, X86::FP1
3690 X86::FP0, X86::FP1
3890 X86::FP0, X86::FP1
gen/lib/Target/X86/X86GenInstrInfo.inc16663 static const MCPhysReg ImplicitList101[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, X86::DF, 0 };
16664 static const MCPhysReg ImplicitList102[] = { X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, X86::DF, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 1220 { X86::FP0 },
1703 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
1943 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2403 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 116 {codeview::RegisterId::ST0, X86::FP0},
lib/Target/X86/X86FastISel.cpp 1217 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3566 if ((SrcReg == X86::FP0 || SrcReg == X86::FP1) &&
lib/Target/X86/X86FloatingPoint.cpp 130 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums");
131 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
132 Mask |= 1 << (Reg - X86::FP0);
317 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
318 return Reg - X86::FP0;
329 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
332 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
471 static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers");
472 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
472 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
473 LLVM_DEBUG(dbgs() << "Register FP#" << Reg - X86::FP0 << " is dead!\n");
474 freeStackSlotAfter(I, Reg-X86::FP0);
981 unsigned R = MO.getReg() - X86::FP0;
1019 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1121 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1182 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1292 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1293 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1387 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1388 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1413 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1478 unsigned Reg = MI.getOperand(0).getReg() - X86::FP0;
1535 unsigned STReg = MO.getReg() - X86::FP0;
1604 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1633 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1702 unsigned Reg = MO.getReg() - X86::FP0;
lib/Target/X86/X86ISelLowering.cpp 2529 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2536 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2541 if (VA.getLocReg() == X86::FP0 ||
2852 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2856 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2862 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
4387 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
45987 return std::make_pair(X86::FP0 + Constraint[4] - '0',
45993 return std::make_pair(X86::FP0, &X86::RFP80RegClass);
unittests/tools/llvm-exegesis/X86/TargetTest.cpp 331 EXPECT_THAT(setRegTo(X86::FP0, APInt(80, "11112222333344445555", 16)),