|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenAsmMatcher.inc 4970 Inst.addOperand(MCOperand::createReg(X86::EAX));
7151 case X86::EAX: OpKind = MCK_EAX; break;
gen/lib/Target/X86/X86GenCallingConv.inc 406 X86::EAX, X86::EDX, X86::ECX
582 if (unsigned Reg = State.AllocateReg(X86::EAX)) {
641 if (unsigned Reg = State.AllocateReg(X86::EAX)) {
736 X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
834 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
1826 if (unsigned Reg = State.AllocateReg(X86::EAX)) {
1900 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
2363 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2700 X86::EAX, X86::EDX, X86::ECX
2969 X86::EAX, X86::EDX, X86::ECX
3001 X86::ESI, X86::EBP, X86::EAX, X86::EDX
3071 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3468 X86::EAX, X86::EDX, X86::ECX, X86::R8D
3641 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
3841 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
gen/lib/Target/X86/X86GenDAGISel.inc18302 /* 36914*/ OPC_EmitCopyToReg, 3, X86::EAX,
18316 /* 36943*/ OPC_EmitCopyToReg, 3, X86::EAX,
18330 /* 36972*/ OPC_EmitCopyToReg, 3, X86::EAX,
18344 /* 37001*/ OPC_EmitCopyToReg, 3, X86::EAX,
18358 /* 37030*/ OPC_EmitCopyToReg, 3, X86::EAX,
18372 /* 37059*/ OPC_EmitCopyToReg, 3, X86::EAX,
18386 /* 37088*/ OPC_EmitCopyToReg, 3, X86::EAX,
18400 /* 37117*/ OPC_EmitCopyToReg, 3, X86::EAX,
18414 /* 37146*/ OPC_EmitCopyToReg, 3, X86::EAX,
18428 /* 37175*/ OPC_EmitCopyToReg, 3, X86::EAX,
18442 /* 37204*/ OPC_EmitCopyToReg, 3, X86::EAX,
18456 /* 37233*/ OPC_EmitCopyToReg, 3, X86::EAX,
18548 /* 37404*/ OPC_EmitCopyToReg, 2, X86::EAX,
18664 /* 37591*/ OPC_EmitCopyToReg, 2, X86::EAX,
18787 /* 37784*/ OPC_EmitCopyToReg, 3, X86::EAX,
58114 /*122750*/ OPC_EmitCopyToReg, 3, X86::EAX,
58128 /*122775*/ OPC_EmitCopyToReg, 3, X86::EAX,
58462 /*123349*/ OPC_EmitCopyToReg, 1, X86::EAX,
gen/lib/Target/X86/X86GenGlobalISel.inc10011 GIR_AddRegister, /*InsnID*/2, X86::EAX, /*AddRegisterRegFlags*/RegState::Define,
10081 GIR_AddRegister, /*InsnID*/2, X86::EAX, /*AddRegisterRegFlags*/RegState::Define,
10104 GIR_AddRegister, /*InsnID*/3, X86::EAX, /*AddRegisterRegFlags*/RegState::Define,
gen/lib/Target/X86/X86GenInstrInfo.inc16566 static const MCPhysReg ImplicitList4[] = { X86::EAX, X86::ECX, X86::EDX, 0 };
16567 static const MCPhysReg ImplicitList5[] = { X86::EAX, X86::EDX, X86::EBX, X86::EFLAGS, 0 };
16569 static const MCPhysReg ImplicitList7[] = { X86::EAX, 0 };
16576 static const MCPhysReg ImplicitList14[] = { X86::EAX, X86::EFLAGS, 0 };
16583 static const MCPhysReg ImplicitList21[] = { X86::EAX, X86::EDX, 0 };
16590 static const MCPhysReg ImplicitList28[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0 };
16591 static const MCPhysReg ImplicitList29[] = { X86::EAX, X86::EDX, X86::EFLAGS, 0 };
16594 static const MCPhysReg ImplicitList32[] = { X86::EAX, X86::ECX, 0 };
16615 static const MCPhysReg ImplicitList53[] = { X86::EAX, X86::ESI, 0 };
16625 static const MCPhysReg ImplicitList63[] = { X86::ECX, X86::EAX, X86::EBX, 0 };
16626 static const MCPhysReg ImplicitList64[] = { X86::ECX, X86::EAX, 0 };
16628 static const MCPhysReg ImplicitList66[] = { X86::DX, X86::EAX, 0 };
16637 static const MCPhysReg ImplicitList75[] = { X86::EDI, X86::ESI, X86::EBP, X86::EBX, X86::EDX, X86::ECX, X86::EAX, X86::ESP, 0 };
16648 static const MCPhysReg ImplicitList86[] = { X86::EAX, X86::ECX, X86::EDI, 0 };
16655 static const MCPhysReg ImplicitList93[] = { X86::EAX, X86::EDI, X86::DF, 0 };
16658 static const MCPhysReg ImplicitList96[] = { X86::EAX, X86::ESP, X86::EFLAGS, 0 };
16661 static const MCPhysReg ImplicitList99[] = { X86::EAX, X86::ECX, X86::EFLAGS, X86::DF, 0 };
16663 static const MCPhysReg ImplicitList101[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::FP7, X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, X86::DF, 0 };
16668 static const MCPhysReg ImplicitList106[] = { X86::EDX, X86::EAX, 0 };
16670 static const MCPhysReg ImplicitList108[] = { X86::EDX, X86::EAX, X86::ECX, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 1593 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP,
1603 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP,
1613 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
1643 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
1653 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
1663 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP,
1673 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
1693 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,
1723 X86::EAX, X86::ECX, X86::EDX, X86::EBX,
1733 X86::EAX, X86::ECX, X86::EDX, X86::ESP,
1743 X86::EAX, X86::ECX, X86::EDX,
1753 X86::EAX, X86::EDX,
2789 { 0U, X86::EAX },
2834 { 0U, X86::EAX },
2956 { 0U, X86::EAX },
3001 { 0U, X86::EAX },
3046 { X86::EAX, -2U },
3196 { X86::EAX, 0U },
3346 { X86::EAX, 0U },
3496 { X86::EAX, -2U },
3646 { X86::EAX, 0U },
3796 { X86::EAX, 0U },
10000 static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
10002 static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
10004 static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
10006 static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
10008 static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
gen/lib/Target/X86/X86GenSubtargetInfo.inc20830 && MI->getOperand(1).getReg() != X86::EAX
22436 && MI->getOperand(1).getReg() != X86::EAX
lib/Target/X86/Disassembler/X86Disassembler.cpp 270 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
507 ALL_REGS
552 ALL_SIB_BASES
567 EA_BASES_32BIT
645 ALL_EA_BASES
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 105 {codeview::RegisterId::EAX, X86::EAX},
618 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
630 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
667 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
703 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
704 return X86::EAX;
739 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp 295 case X86::EAX: OS << "$eax"; break;
lib/Target/X86/X86CallingConv.cpp 33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI,
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX};
lib/Target/X86/X86FastISel.cpp 1269 unsigned RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
1893 { &X86::GR32RegClass, X86::EAX, X86::EDX, {
1894 { X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S }, // SDiv
1896 { X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U }, // UDiv
2947 static const MCPhysReg Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX };
lib/Target/X86/X86FrameLowering.cpp 200 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
264 unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
325 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
797 unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX;
1257 .addReg(X86::EAX, RegState::Kill)
1267 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1282 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1297 MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
2157 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2277 return Primary ? X86::EAX : X86::ECX;
2280 return Primary ? X86::EDX : X86::EAX;
2281 return Primary ? X86::ECX : X86::EAX;
2461 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
lib/Target/X86/X86ISelDAGToDAG.cpp 4392 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX;
4644 LoReg = X86::EAX;
4729 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
4833 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
5151 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::EAX,
lib/Target/X86/X86ISelLowering.cpp 2632 X86::RAX : X86::EAX;
4463 case X86::EAX: case X86::EDX: case X86::ECX:
17976 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
18007 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
18153 unsigned Reg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
23824 LO = DAG.getCopyFromReg(Chain, DL, X86::EAX, MVT::i32, SDValue(N1, 1));
24294 return Subtarget.isTarget64BitLP64() ? X86::RAX : X86::EAX;
24477 NestReg = X86::EAX;
26699 case MVT::i32: Reg = X86::EAX; size = 4; break;
28290 Regs64bit ? X86::RAX : X86::EAX,
28344 Regs64bit ? X86::RAX : X86::EAX,
29237 .addReg(X86::EAX);
30106 .addReg(X86::EAX, RegState::ImplicitDefine);
30114 .addReg(X86::EAX, RegState::ImplicitDefine);
30122 .addReg(IsLP64 ? X86::RAX : X86::EAX);
30258 BuildMI(*BB, MI, DL, TII->get(X86::MOV32rm), X86::EAX)
30266 addDirectMem(MIB, X86::EAX);
30267 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
30270 BuildMI(*BB, MI, DL, TII->get(X86::MOV32rm), X86::EAX)
30278 addDirectMem(MIB, X86::EAX);
30279 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
30317 case X86::EAX:
30338 case X86::EAX:
30377 AvailableRegs.append({X86::EAX, X86::ECX, X86::EDX, X86::EDI});
31391 while (RMBBI != BB->rend() && (RMBBI->definesRegister(X86::EAX) ||
45803 return std::make_pair(X86::EAX, &X86::GR32_ADRegClass);
46057 return std::make_pair(X86::EAX, &X86::GR32_ADRegClass);
lib/Target/X86/X86InstrInfo.cpp 7908 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7936 .addReg(is64Bit ? X86::RAX : X86::EAX);
lib/Target/X86/X86InstructionSelector.cpp 1586 X86::EAX,
1589 {X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S}, // SDiv
1591 {X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U}, // UDiv
lib/Target/X86/X86MCInstLower.cpp 303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
326 if (Op0 == X86::EAX && Op1 == X86::AX)
330 if (Op0 == X86::RAX && Op1 == X86::EAX)
364 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
739 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
951 .addReg(X86::EAX)
959 .addReg(X86::EAX)
lib/Target/X86/X86RetpolineThunks.cpp 181 populateThunk(MF, X86::EAX);
lib/Target/X86/X86SelectionDAGInfo.cpp 57 X86::ECX, X86::EAX, X86::EDI};
122 ValReg = X86::EAX;
lib/Target/X86/X86WinAllocaExpander.cpp 219 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX;
233 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX;
247 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX;
unittests/tools/llvm-exegesis/X86/AssemblerTest.cpp 45 Check({{EAX, APInt(32, 1)}},
46 MCInstBuilder(XOR32rr).addReg(EAX).addReg(EAX).addReg(EAX),
46 MCInstBuilder(XOR32rr).addReg(EAX).addReg(EAX).addReg(EAX),
46 MCInstBuilder(XOR32rr).addReg(EAX).addReg(EAX).addReg(EAX),
59 Check({}, MCInstBuilder(MOV32ri).addReg(EAX).addImm(42), 0xb8, 0x2a, 0x00,
unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp 30 const RegisterAliasingTracker tracker(RegInfo, X86::EAX);
35 X86::AL, X86::AH, X86::AX, X86::EAX, X86::HAX, X86::RAX};
38 ASSERT_THAT(tracker.getOrigin(aliased), X86::EAX);
unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp 47 FunctionFiller Sink(*MF, {X86::EAX});
88 LiveReg(X86::EAX),