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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenAsmMatcher.inc 7090 case X86::AH: OpKind = MCK_GR8_ABCD_H; break;
gen/lib/Target/X86/X86GenDAGISel.inc58052 /*122642*/ OPC_EmitCopyToReg, 0, X86::AH,
gen/lib/Target/X86/X86GenInstrInfo.inc16598 static const MCPhysReg ImplicitList36[] = { X86::AL, X86::AH, X86::EFLAGS, 0 };
16610 static const MCPhysReg ImplicitList48[] = { X86::AH, 0 };
gen/lib/Target/X86/X86GenRegisterInfo.inc 1145 { X86::AH },
1313 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
1333 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
1343 X86::AH, X86::CH, X86::DH, X86::BH,
lib/Target/X86/Disassembler/X86Disassembler.cpp 270 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
507 ALL_REGS
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp 1068 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 93 {codeview::RegisterId::AH, X86::AH},
618 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
619 return X86::AH;
630 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
667 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
703 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
739 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
lib/Target/X86/X86FastISel.cpp 1881 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S }, // SRem
1883 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U }, // URem
1987 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) {
lib/Target/X86/X86FrameLowering.cpp 201 Reg == X86::AH || Reg == X86::AL)
lib/Target/X86/X86ISelDAGToDAG.cpp 4824 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
4932 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) {
4933 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);
lib/Target/X86/X86InstructionSelector.cpp 1572 {X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S}, // SRem
1574 {X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U}, // URem
1689 OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) {
tools/llvm-exegesis/lib/X86/Target.cpp 583 const unsigned ExegesisX86Target::kUnavailableRegisters[4] = {X86::AH, X86::BH,
unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp 68 .addReg(X86::AH)
74 RegisterValue{X86::AH, APInt(8, "123", 10)}};
unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp 35 X86::AL, X86::AH, X86::AX, X86::EAX, X86::HAX, X86::RAX};
unittests/tools/llvm-exegesis/X86/TargetTest.cpp 141 EXPECT_TRUE(State.getRATC().reservedRegisters().test(X86::AH));