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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc18048 { 360, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #360 = ADD_Fp64m
18049 { 361, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #361 = ADD_Fp64m32
18054 { 366, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #366 = ADD_FpI16m64
18057 { 369, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #369 = ADD_FpI32m64
18564 { 876, 7, 1, 0, 125, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #876 = DIVR_Fp64m
18565 { 877, 7, 1, 0, 125, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #877 = DIVR_Fp64m32
18569 { 881, 7, 1, 0, 125, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #881 = DIVR_FpI16m64
18572 { 884, 7, 1, 0, 125, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #884 = DIVR_FpI32m64
18592 { 904, 7, 1, 0, 125, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #904 = DIV_Fp64m
18593 { 905, 7, 1, 0, 125, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #905 = DIV_Fp64m32
18598 { 910, 7, 1, 0, 125, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #910 = DIV_FpI16m64
18601 { 913, 7, 1, 0, 125, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #913 = DIV_FpI32m64
19561 { 1873, 7, 1, 0, 236, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #1873 = MUL_Fp64m
19562 { 1874, 7, 1, 0, 236, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #1874 = MUL_Fp64m32
19567 { 1879, 7, 1, 0, 236, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #1879 = MUL_FpI16m64
19570 { 1882, 7, 1, 0, 236, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #1882 = MUL_FpI32m64
20496 { 2808, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #2808 = SUBR_Fp64m
20497 { 2809, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #2809 = SUBR_Fp64m32
20501 { 2813, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #2813 = SUBR_FpI16m64
20504 { 2816, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #2816 = SUBR_FpI32m64
20524 { 2836, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #2836 = SUB_Fp64m
20525 { 2837, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #2837 = SUB_Fp64m32
20530 { 2842, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #2842 = SUB_FpI16m64
20533 { 2845, 7, 1, 0, 29, 0|(1ULL<<MCID::MayLoad), 0x600000ULL, ImplicitList12, ImplicitList13, OperandInfo96, -1 ,nullptr }, // Inst #2845 = SUB_FpI32m64