|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/X86/X86GenInstrInfo.inc18039 { 351, 5, 0, 0, 773, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3600000028ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #351 = ADD_F32m
18040 { 352, 5, 0, 0, 773, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3700000028ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #352 = ADD_F64m
18041 { 353, 5, 0, 0, 777, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3780000028ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #353 = ADD_FI16m
18042 { 354, 5, 0, 0, 777, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3680000028ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #354 = ADD_FI32m
18277 { 589, 5, 0, 0, 761, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad), 0x3fc00000aaULL, ImplicitList17, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #589 = CALL16m
18278 { 590, 5, 0, 0, 761, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad), 0x20003fc00000aaULL, ImplicitList17, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #590 = CALL16m_NT
18281 { 593, 5, 0, 0, 761, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad), 0x3fc000012aULL, ImplicitList17, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #593 = CALL32m
18282 { 594, 5, 0, 0, 761, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad), 0x20003fc000012aULL, ImplicitList17, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #594 = CALL32m_NT
18285 { 597, 5, 0, 0, 762, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad), 0x3fc000002aULL, ImplicitList6, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #597 = CALL64m
18286 { 598, 5, 0, 0, 762, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad), 0x20003fc000002aULL, ImplicitList6, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #598 = CALL64m_NT
18304 { 616, 5, 0, 0, 858, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x700002028ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #616 = CLDEMOTE
18306 { 618, 5, 0, 0, 742, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000202fULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #618 = CLFLUSH
18307 { 619, 5, 0, 0, 742, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000282fULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #619 = CLFLUSHOPT
18310 { 622, 5, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000302eULL, nullptr, ImplicitList23, OperandInfo91, -1 ,nullptr }, // Inst #622 = CLRSSBSY
18312 { 624, 5, 0, 0, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000282eULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #624 = CLWB
18427 { 739, 5, 0, 0, 671, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x31c0012029ULL, ImplicitList26, ImplicitList27, OperandInfo91, -1 ,nullptr }, // Inst #739 = CMPXCHG16B
18434 { 746, 5, 0, 0, 665, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x31c0002029ULL, ImplicitList28, ImplicitList29, OperandInfo91, -1 ,nullptr }, // Inst #746 = CMPXCHG8B
18535 { 847, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc00000a9ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #847 = DEC16m
18538 { 850, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc0000129ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #850 = DEC32m
18541 { 853, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc0010029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #853 = DEC64m
18543 { 855, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3f80000029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #855 = DEC8m
18545 { 857, 5, 0, 0, 113, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc00000aeULL, ImplicitList34, ImplicitList35, OperandInfo91, -1 ,nullptr }, // Inst #857 = DIV16m
18547 { 859, 5, 0, 0, 115, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc000012eULL, ImplicitList21, ImplicitList29, OperandInfo91, -1 ,nullptr }, // Inst #859 = DIV32m
18549 { 861, 5, 0, 0, 117, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc001002eULL, ImplicitList33, ImplicitList27, OperandInfo91, -1 ,nullptr }, // Inst #861 = DIV64m
18551 { 863, 5, 0, 0, 119, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3d8000002eULL, ImplicitList10, ImplicitList36, OperandInfo91, -1 ,nullptr }, // Inst #863 = DIV8m
18557 { 869, 5, 0, 0, 903, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x360000002fULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #869 = DIVR_F32m
18558 { 870, 5, 0, 0, 903, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x370000002fULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #870 = DIVR_F64m
18559 { 871, 5, 0, 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x378000002fULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #871 = DIVR_FI16m
18560 { 872, 5, 0, 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x368000002fULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #872 = DIVR_FI32m
18583 { 895, 5, 0, 0, 779, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x360000002eULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #895 = DIV_F32m
18584 { 896, 5, 0, 0, 779, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x370000002eULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #896 = DIV_F64m
18585 { 897, 5, 0, 0, 780, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x378000002eULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #897 = DIV_FI16m
18586 { 898, 5, 0, 0, 780, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x368000002eULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #898 = DIV_FI32m
18612 { 924, 5, 0, 0, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #924 = EH_SjLj_LongJmp32
18613 { 925, 5, 0, 0, 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #925 = EH_SjLj_LongJmp64
18636 { 948, 5, 0, 0, 5, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00000abULL, ImplicitList17, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #948 = FARCALL16m
18638 { 950, 5, 0, 0, 5, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc000012bULL, ImplicitList17, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #950 = FARCALL32m
18639 { 951, 5, 0, 0, 767, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc001002bULL, ImplicitList6, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #951 = FARCALL64
18641 { 953, 5, 0, 0, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00000adULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #953 = FARJMP16m
18643 { 955, 5, 0, 0, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc000012dULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #955 = FARJMP32m
18644 { 956, 5, 0, 0, 758, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc001002dULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #956 = FARJMP64
18645 { 957, 5, 0, 0, 800, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x37c000002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #957 = FBLDm
18646 { 958, 5, 0, 0, 810, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x37c000002eULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #958 = FBSTPm
18647 { 959, 5, 0, 0, 927, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x360000002aULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #959 = FCOM32m
18648 { 960, 5, 0, 0, 927, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x370000002aULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #960 = FCOM64m
18649 { 961, 5, 0, 0, 927, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x360000002bULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #961 = FCOMP32m
18650 { 962, 5, 0, 0, 927, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x370000002bULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #962 = FCOMP64m
18656 { 968, 5, 0, 0, 775, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x378000002aULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #968 = FICOM16m
18657 { 969, 5, 0, 0, 775, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x368000002aULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #969 = FICOM32m
18658 { 970, 5, 0, 0, 775, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x378000002bULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #970 = FICOMP16m
18659 { 971, 5, 0, 0, 775, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x368000002bULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #971 = FICOMP32m
18661 { 973, 5, 0, 0, 632, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x364000002dULL, nullptr, ImplicitList38, OperandInfo91, -1 ,nullptr }, // Inst #973 = FLDCW16m
18662 { 974, 5, 0, 0, 910, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x364000002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #974 = FLDENVm
18671 { 983, 5, 0, 0, 648, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x364000002fULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #983 = FNSTCW16m
18673 { 985, 5, 0, 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x374000002fULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #985 = FNSTSWm
18688 { 1000, 5, 0, 0, 803, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x374000002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1000 = FRSTORm
18689 { 1001, 5, 0, 0, 802, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x374000002eULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1001 = FSAVEm
18692 { 1004, 5, 0, 0, 912, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x364000002eULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1004 = FSTENVm
18695 { 1007, 5, 0, 0, 701, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b80002029ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1007 = FXRSTOR
18696 { 1008, 5, 0, 0, 911, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b80012029ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1008 = FXRSTOR64
18697 { 1009, 5, 0, 0, 700, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b80002028ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1009 = FXSAVE
18698 { 1010, 5, 0, 0, 700, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b80012028ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1010 = FXSAVE64
18719 { 1031, 5, 0, 0, 144, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc00000afULL, ImplicitList34, ImplicitList35, OperandInfo91, -1 ,nullptr }, // Inst #1031 = IDIV16m
18721 { 1033, 5, 0, 0, 146, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc000012fULL, ImplicitList21, ImplicitList29, OperandInfo91, -1 ,nullptr }, // Inst #1033 = IDIV32m
18723 { 1035, 5, 0, 0, 148, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc001002fULL, ImplicitList33, ImplicitList27, OperandInfo91, -1 ,nullptr }, // Inst #1035 = IDIV64m
18725 { 1037, 5, 0, 0, 150, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3d8000002fULL, ImplicitList10, ImplicitList36, OperandInfo91, -1 ,nullptr }, // Inst #1037 = IDIV8m
18727 { 1039, 5, 0, 0, 598, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x37c0000028ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1039 = ILD_F16m
18728 { 1040, 5, 0, 0, 598, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x36c0000028ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1040 = ILD_F32m
18729 { 1041, 5, 0, 0, 598, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x37c000002dULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1041 = ILD_F64m
18739 { 1051, 5, 0, 0, 152, 0|(1ULL<<MCID::MayLoad), 0x3dc00000adULL, ImplicitList10, ImplicitList35, OperandInfo91, -1 ,nullptr }, // Inst #1051 = IMUL16m
18747 { 1059, 5, 0, 0, 158, 0|(1ULL<<MCID::MayLoad), 0x3dc000012dULL, ImplicitList7, ImplicitList29, OperandInfo91, -1 ,nullptr }, // Inst #1059 = IMUL32m
18755 { 1067, 5, 0, 0, 164, 0|(1ULL<<MCID::MayLoad), 0x3dc001002dULL, ImplicitList16, ImplicitList27, OperandInfo91, -1 ,nullptr }, // Inst #1067 = IMUL64m
18763 { 1075, 5, 0, 0, 170, 0|(1ULL<<MCID::MayLoad), 0x3d8000002dULL, ImplicitList11, ImplicitList40, OperandInfo91, -1 ,nullptr }, // Inst #1075 = IMUL8m
18771 { 1083, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc00000a8ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1083 = INC16m
18774 { 1086, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc0000128ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1086 = INC32m
18777 { 1089, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc0010028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1089 = INC64m
18779 { 1091, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3f80000028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1091 = INC8m
18796 { 1108, 5, 0, 0, 688, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000202fULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1108 = INVLPG
18807 { 1119, 5, 0, 0, 735, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x37c0000029ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1119 = ISTT_FP16m
18808 { 1120, 5, 0, 0, 735, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x36c0000029ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1120 = ISTT_FP32m
18809 { 1121, 5, 0, 0, 735, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x3740000029ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1121 = ISTT_FP64m
18819 { 1131, 5, 0, 0, 642, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x37c000002aULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1131 = IST_F16m
18820 { 1132, 5, 0, 0, 642, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x36c000002aULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1132 = IST_F32m
18821 { 1133, 5, 0, 0, 642, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x37c000002bULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1133 = IST_FP16m
18822 { 1134, 5, 0, 0, 642, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x36c000002bULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1134 = IST_FP32m
18823 { 1135, 5, 0, 0, 642, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x37c000002fULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1135 = IST_FP64m
18840 { 1152, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x3fc00000acULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1152 = JMP16m
18841 { 1153, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20003fc00000acULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1153 = JMP16m_NT
18844 { 1156, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x3fc000012cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1156 = JMP32m
18845 { 1157, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20003fc000012cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1157 = JMP32m_NT
18848 { 1160, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x3fc000002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1160 = JMP64m
18849 { 1161, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20003fc000002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1161 = JMP64m_NT
18850 { 1162, 5, 0, 0, 831, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc001002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1162 = JMP64m_REX
18933 { 1245, 5, 0, 0, 1048, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x31c1012029ULL, ImplicitList26, ImplicitList27, OperandInfo91, -1 ,nullptr }, // Inst #1245 = LCMPXCHG16B
18937 { 1249, 5, 0, 0, 1048, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x31c1002029ULL, ImplicitList28, ImplicitList29, OperandInfo91, -1 ,nullptr }, // Inst #1249 = LCMPXCHG8B
18939 { 1251, 5, 0, 0, 178, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000202aULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1251 = LDMXCSR
18944 { 1256, 5, 0, 0, 770, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3640000028ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1256 = LD_F32m
18945 { 1257, 5, 0, 0, 770, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3740000028ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1257 = LD_F64m
18946 { 1258, 5, 0, 0, 629, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x36c000002dULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1258 = LD_F80m
18972 { 1284, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400020aaULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1284 = LGDT16m
18973 { 1285, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000212aULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1285 = LGDT32m
18974 { 1286, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000202aULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1286 = LGDT64m
18978 { 1290, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400020abULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1290 = LIDT16m
18979 { 1291, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000212bULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1291 = LIDT32m
18980 { 1292, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000202bULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1292 = LIDT64m
18981 { 1293, 5, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x202aULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1293 = LLDT16m
18985 { 1297, 5, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000202eULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1297 = LMSW16m
19009 { 1321, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc10000a9ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1321 = LOCK_DEC16m
19010 { 1322, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc1000129ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1322 = LOCK_DEC32m
19011 { 1323, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc1010029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1323 = LOCK_DEC64m
19012 { 1324, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3f81000029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1324 = LOCK_DEC8m
19013 { 1325, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc10000a8ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1325 = LOCK_INC16m
19014 { 1326, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc1000128ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1326 = LOCK_INC32m
19015 { 1327, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc1010028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1327 = LOCK_INC64m
19016 { 1328, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3f81000028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1328 = LOCK_INC8m
19073 { 1385, 5, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x202bULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1385 = LTRm
19528 { 1840, 5, 0, 0, 152, 0|(1ULL<<MCID::MayLoad), 0x3dc00000acULL, ImplicitList10, ImplicitList35, OperandInfo91, -1 ,nullptr }, // Inst #1840 = MUL16m
19530 { 1842, 5, 0, 0, 158, 0|(1ULL<<MCID::MayLoad), 0x3dc000012cULL, ImplicitList7, ImplicitList29, OperandInfo91, -1 ,nullptr }, // Inst #1842 = MUL32m
19532 { 1844, 5, 0, 0, 164, 0|(1ULL<<MCID::MayLoad), 0x3dc001002cULL, ImplicitList16, ImplicitList27, OperandInfo91, -1 ,nullptr }, // Inst #1844 = MUL64m
19534 { 1846, 5, 0, 0, 170, 0|(1ULL<<MCID::MayLoad), 0x3d8000002cULL, ImplicitList11, ImplicitList40, OperandInfo91, -1 ,nullptr }, // Inst #1846 = MUL8m
19552 { 1864, 5, 0, 0, 776, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3600000029ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1864 = MUL_F32m
19553 { 1865, 5, 0, 0, 776, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3700000029ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1865 = MUL_F64m
19554 { 1866, 5, 0, 0, 778, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3780000029ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1866 = MUL_FI16m
19555 { 1867, 5, 0, 0, 778, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3680000029ULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #1867 = MUL_FI32m
19575 { 1887, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3dc00000abULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1887 = NEG16m
19577 { 1889, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3dc000012bULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1889 = NEG32m
19579 { 1891, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3dc001002bULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1891 = NEG64m
19581 { 1893, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3d8000002bULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1893 = NEG8m
19584 { 1896, 5, 0, 0, 80, 0, 0x7c0002127ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1896 = NOOPL
19586 { 1898, 5, 0, 0, 80, 0, 0x7c0012027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1898 = NOOPQ
19588 { 1900, 5, 0, 0, 80, 0, 0x7c00020a7ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1900 = NOOPW
19590 { 1902, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3dc00000aaULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1902 = NOT16m
19592 { 1904, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3dc000012aULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1904 = NOT32m
19594 { 1906, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3dc001002aULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1906 = NOT64m
19596 { 1908, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3d8000002aULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1908 = NOT8m
19873 { 2185, 5, 0, 0, 940, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c00000a8ULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2185 = POP16rmm
19876 { 2188, 5, 0, 0, 619, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c0000128ULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2188 = POP32rmm
19879 { 2191, 5, 0, 0, 619, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c0000128ULL, ImplicitList74, ImplicitList74, OperandInfo91, -1 ,nullptr }, // Inst #2191 = POP64rmm
19906 { 2218, 5, 0, 0, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x340002028ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2218 = PREFETCH
19907 { 2219, 5, 0, 0, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x600002028ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2219 = PREFETCHNTA
19908 { 2220, 5, 0, 0, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x600002029ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2220 = PREFETCHT0
19909 { 2221, 5, 0, 0, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x60000202aULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2221 = PREFETCHT1
19910 { 2222, 5, 0, 0, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x60000202bULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2222 = PREFETCHT2
19911 { 2223, 5, 0, 0, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x340002029ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2223 = PREFETCHW
19912 { 2224, 5, 0, 0, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34000202aULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2224 = PREFETCHWT1
19975 { 2287, 5, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8001302cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2287 = PTWRITE64m
19977 { 2289, 5, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000302cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2289 = PTWRITEm
19997 { 2309, 5, 0, 0, 941, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc00000aeULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2309 = PUSH16rmm
20001 { 2313, 5, 0, 0, 941, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc000012eULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2313 = PUSH32rmm
20006 { 2318, 5, 0, 0, 606, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc000012eULL, ImplicitList74, ImplicitList74, OperandInfo91, -1 ,nullptr }, // Inst #2318 = PUSH64rmm
20031 { 2343, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x34400000aaULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2343 = RCL16m1
20032 { 2344, 5, 0, 0, 897, 0|(1ULL<<MCID::MayStore), 0x34c00000aaULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2344 = RCL16mCL
20037 { 2349, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344000012aULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2349 = RCL32m1
20038 { 2350, 5, 0, 0, 897, 0|(1ULL<<MCID::MayStore), 0x34c000012aULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2350 = RCL32mCL
20043 { 2355, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344001002aULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2355 = RCL64m1
20044 { 2356, 5, 0, 0, 897, 0|(1ULL<<MCID::MayStore), 0x34c001002aULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2356 = RCL64mCL
20049 { 2361, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x340000002aULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2361 = RCL8m1
20050 { 2362, 5, 0, 0, 897, 0|(1ULL<<MCID::MayStore), 0x348000002aULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2362 = RCL8mCL
20061 { 2373, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x34400000abULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2373 = RCR16m1
20062 { 2374, 5, 0, 0, 584, 0|(1ULL<<MCID::MayStore), 0x34c00000abULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2374 = RCR16mCL
20067 { 2379, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344000012bULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2379 = RCR32m1
20068 { 2380, 5, 0, 0, 584, 0|(1ULL<<MCID::MayStore), 0x34c000012bULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2380 = RCR32mCL
20073 { 2385, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344001002bULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2385 = RCR64m1
20074 { 2386, 5, 0, 0, 584, 0|(1ULL<<MCID::MayStore), 0x34c001002bULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2386 = RCR64mCL
20079 { 2391, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x340000002bULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2391 = RCR8m1
20080 { 2392, 5, 0, 0, 584, 0|(1ULL<<MCID::MayStore), 0x348000002bULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2392 = RCR8mCL
20132 { 2444, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34400000a8ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2444 = ROL16m1
20133 { 2445, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000a8ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2445 = ROL16mCL
20138 { 2450, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3440000128ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2450 = ROL32m1
20139 { 2451, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0000128ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2451 = ROL32mCL
20144 { 2456, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3440010028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2456 = ROL64m1
20145 { 2457, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0010028ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2457 = ROL64mCL
20150 { 2462, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3400000028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2462 = ROL8m1
20151 { 2463, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3480000028ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2463 = ROL8mCL
20156 { 2468, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34400000a9ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2468 = ROR16m1
20157 { 2469, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000a9ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2469 = ROR16mCL
20162 { 2474, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3440000129ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2474 = ROR32m1
20163 { 2475, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0000129ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2475 = ROR32mCL
20168 { 2480, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3440010029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2480 = ROR64m1
20169 { 2481, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0010029ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2481 = ROR64mCL
20174 { 2486, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3400000029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2486 = ROR8m1
20175 { 2487, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3480000029ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2487 = ROR8mCL
20203 { 2515, 5, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000302dULL, ImplicitList23, ImplicitList23, OperandInfo91, -1 ,nullptr }, // Inst #2515 = RSTORSSP
20206 { 2518, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34400000afULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2518 = SAR16m1
20207 { 2519, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000afULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2519 = SAR16mCL
20212 { 2524, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344000012fULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2524 = SAR32m1
20213 { 2525, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c000012fULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2525 = SAR32mCL
20218 { 2530, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344001002fULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2530 = SAR64m1
20219 { 2531, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c001002fULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2531 = SAR64mCL
20224 { 2536, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x340000002fULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2536 = SAR8m1
20225 { 2537, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x348000002fULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2537 = SAR8mCL
20281 { 2593, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400020a8ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2593 = SGDT16m
20282 { 2594, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40002128ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2594 = SGDT32m
20283 { 2595, 5, 0, 0, 822, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40002028ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2595 = SGDT64m
20298 { 2610, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34400000acULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2610 = SHL16m1
20299 { 2611, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000acULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2611 = SHL16mCL
20304 { 2616, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344000012cULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2616 = SHL32m1
20305 { 2617, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c000012cULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2617 = SHL32mCL
20310 { 2622, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344001002cULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2622 = SHL64m1
20311 { 2623, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c001002cULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2623 = SHL64mCL
20316 { 2628, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x340000002cULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2628 = SHL8m1
20317 { 2629, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x348000002cULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2629 = SHL8mCL
20338 { 2650, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34400000adULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2650 = SHR16m1
20339 { 2651, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000adULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2651 = SHR16mCL
20344 { 2656, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344000012dULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2656 = SHR32m1
20345 { 2657, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c000012dULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2657 = SHR32mCL
20350 { 2662, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344001002dULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2662 = SHR64m1
20351 { 2663, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c001002dULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2663 = SHR64mCL
20356 { 2668, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x340000002dULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2668 = SHR8m1
20357 { 2669, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x348000002dULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2669 = SHR8mCL
20382 { 2694, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400020a9ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2694 = SIDT16m
20383 { 2695, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40002129ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2695 = SIDT32m
20384 { 2696, 5, 0, 0, 822, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40002029ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2696 = SIDT64m
20390 { 2702, 5, 0, 0, 8, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2028ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2702 = SLDT16m
20396 { 2708, 5, 0, 0, 822, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000202cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2708 = SMSW16m
20422 { 2734, 5, 0, 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000202bULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2734 = STMXCSR
20430 { 2742, 5, 0, 0, 822, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2029ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2742 = STRm
20431 { 2743, 5, 0, 0, 609, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x364000002aULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2743 = ST_F32m
20432 { 2744, 5, 0, 0, 609, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x374000002aULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2744 = ST_F64m
20433 { 2745, 5, 0, 0, 812, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x364000002bULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2745 = ST_FP32m
20434 { 2746, 5, 0, 0, 812, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x374000002bULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2746 = ST_FP64m
20435 { 2747, 5, 0, 0, 633, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x36c000002fULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2747 = ST_FP80m
20489 { 2801, 5, 0, 0, 773, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x360000002dULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2801 = SUBR_F32m
20490 { 2802, 5, 0, 0, 773, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x370000002dULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2802 = SUBR_F64m
20491 { 2803, 5, 0, 0, 777, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x378000002dULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2803 = SUBR_FI16m
20492 { 2804, 5, 0, 0, 777, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x368000002dULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2804 = SUBR_FI32m
20515 { 2827, 5, 0, 0, 773, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x360000002cULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2827 = SUB_F32m
20516 { 2828, 5, 0, 0, 773, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x370000002cULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2828 = SUB_F64m
20517 { 2829, 5, 0, 0, 777, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x378000002cULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2829 = SUB_FI16m
20518 { 2830, 5, 0, 0, 777, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x368000002cULL, ImplicitList12, ImplicitList13, OperandInfo91, -1 ,nullptr }, // Inst #2830 = SUB_FI32m
20585 { 2897, 5, 0, 0, 8, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList17, ImplicitList99, OperandInfo91, -1 ,nullptr }, // Inst #2897 = TLSCall_32
20586 { 2898, 5, 0, 0, 8, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, ImplicitList100, OperandInfo91, -1 ,nullptr }, // Inst #2898 = TLSCall_64
20587 { 2899, 5, 0, 0, 8, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList17, ImplicitList101, OperandInfo91, -1 ,nullptr }, // Inst #2899 = TLS_addr32
20588 { 2900, 5, 0, 0, 8, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, ImplicitList102, OperandInfo91, -1 ,nullptr }, // Inst #2900 = TLS_addr64
20589 { 2901, 5, 0, 0, 8, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList17, ImplicitList101, OperandInfo91, -1 ,nullptr }, // Inst #2901 = TLS_base_addr32
20590 { 2902, 5, 0, 0, 8, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, ImplicitList102, OperandInfo91, -1 ,nullptr }, // Inst #2902 = TLS_base_addr64
22503 { 4815, 5, 0, 0, 757, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x202cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #4815 = VERRm
22505 { 4817, 5, 0, 0, 757, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x202dULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #4817 = VERWm
24903 { 7215, 5, 0, 0, 178, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b9400202aULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #7215 = VLDMXCSR
25083 { 7395, 5, 0, 0, 909, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c000282eULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #7395 = VMCLEARm
25815 { 8127, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c000202eULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #8127 = VMPTRLDm
25816 { 8128, 5, 0, 0, 811, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c000202fULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #8128 = VMPTRSTm
25929 { 8241, 5, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c000302eULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #8241 = VMXON
32512 { 14824, 5, 0, 0, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b9400202bULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #14824 = VSTMXCSR
32916 { 15228, 5, 0, 0, 901, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000202dULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15228 = XRSTOR
32917 { 15229, 5, 0, 0, 901, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8001202dULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15229 = XRSTOR64
32918 { 15230, 5, 0, 0, 901, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x31c000202bULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15230 = XRSTORS
32919 { 15231, 5, 0, 0, 901, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x31c001202bULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15231 = XRSTORS64
32920 { 15232, 5, 0, 0, 907, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000202cULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15232 = XSAVE
32921 { 15233, 5, 0, 0, 906, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8001202cULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15233 = XSAVE64
32922 { 15234, 5, 0, 0, 1074, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x31c000202cULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15234 = XSAVEC
32923 { 15235, 5, 0, 0, 1074, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x31c001202cULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15235 = XSAVEC64
32924 { 15236, 5, 0, 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000202eULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15236 = XSAVEOPT
32925 { 15237, 5, 0, 0, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8001202eULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15237 = XSAVEOPT64
32926 { 15238, 5, 0, 0, 1074, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x31c000202dULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15238 = XSAVES
32927 { 15239, 5, 0, 0, 1074, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x31c001202dULL, ImplicitList106, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #15239 = XSAVES64