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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17968 { 280, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x440010020ULL, ImplicitList1, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #280 = ADC64mr
18008 { 320, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x40010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #320 = ADD64mr
18101 { 413, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x840010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #413 = AND64mr
18234 { 546, 6, 0, 0, 55, 0|(1ULL<<MCID::MayLoad), 0x28c0012020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #546 = BT64mr
18246 { 558, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ec0012020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #558 = BTC64mr
18258 { 570, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2cc0012020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #570 = BTR64mr
18270 { 582, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ac0012020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #582 = BTS64mr
18396 { 708, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xe40010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #708 = CMP64mr
18432 { 744, 6, 0, 0, 662, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2c40012020ULL, ImplicitList16, ImplicitList15, OperandInfo81, -1 ,nullptr }, // Inst #744 = CMPXCHG64rm
18935 { 1247, 6, 0, 0, 1046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2c41012020ULL, ImplicitList16, ImplicitList15, OperandInfo81, -1 ,nullptr }, // Inst #1247 = LCMPXCHG64
18995 { 1307, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x41010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1307 = LOCK_ADD64mr
19006 { 1318, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x841010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1318 = LOCK_AND64mr
19025 { 1337, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x241010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1337 = LOCK_OR64mr
19037 { 1349, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa41010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1349 = LOCK_SUB64mr
19048 { 1360, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc41010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1360 = LOCK_XOR64mr
19372 { 1684, 6, 0, 0, 134, 0|(1ULL<<MCID::MayStore), 0x2240010020ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1684 = MOV64mr
19415 { 1727, 6, 0, 0, 839, 0|(1ULL<<MCID::MayStore), 0x3c40014020ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1727 = MOVBE64mr
19426 { 1738, 6, 0, 0, 134, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x3e40014020ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1738 = MOVDIRI64
19449 { 1761, 6, 0, 0, 218, 0|(1ULL<<MCID::MayStore), 0x30c0012020ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1761 = MOVNTI_64mr
19620 { 1932, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x240010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1932 = OR64mr
20256 { 2568, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x640010020ULL, ImplicitList1, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2568 = SBB64mr
20330 { 2642, 6, 0, 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2940012020ULL, ImplicitList90, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2642 = SHLD64mrCL
20370 { 2682, 6, 0, 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b40012020ULL, ImplicitList90, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2682 = SHRD64mrCL
20470 { 2782, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa40010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2782 = SUB64mr
20577 { 2889, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x2140010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2889 = TEST64mr
25819 { 8131, 6, 0, 0, 8, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1e00002020ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #8131 = VMREAD64mr
32839 { 15151, 6, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x3d80014020ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #15151 = WRSSQ
32841 { 15153, 6, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x3d40014820ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #15153 = WRUSSQ
32896 { 15208, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc40010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #15208 = XOR64mr