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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17950 { 262, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4400000a0ULL, ImplicitList1, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #262 = ADC16mr
17990 { 302, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #302 = ADD16mr
18083 { 395, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #395 = AND16mr
18128 { 440, 6, 0, 0, 672, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x18c0000020ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #440 = ARPL16mr
18226 { 538, 6, 0, 0, 55, 0|(1ULL<<MCID::MayLoad), 0x28c00020a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #538 = BT16mr
18238 { 550, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ec00020a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #550 = BTC16mr
18250 { 562, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2cc00020a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #562 = BTR16mr
18262 { 574, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ac00020a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #574 = BTS16mr
18378 { 690, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xe400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #690 = CMP16mr
18428 { 740, 6, 0, 0, 662, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2c400020a0ULL, ImplicitList10, ImplicitList9, OperandInfo77, -1 ,nullptr }, // Inst #740 = CMPXCHG16rm
18932 { 1244, 6, 0, 0, 1046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2c410020a0ULL, ImplicitList10, ImplicitList9, OperandInfo77, -1 ,nullptr }, // Inst #1244 = LCMPXCHG16
18989 { 1301, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x410000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1301 = LOCK_ADD16mr
19000 { 1312, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8410000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1312 = LOCK_AND16mr
19019 { 1331, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2410000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1331 = LOCK_OR16mr
19031 { 1343, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa410000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1343 = LOCK_SUB16mr
19042 { 1354, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc410000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1354 = LOCK_XOR16mr
19335 { 1647, 6, 0, 0, 134, 0|(1ULL<<MCID::MayStore), 0x22400000a0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #1647 = MOV16mr
19411 { 1723, 6, 0, 0, 840, 0|(1ULL<<MCID::MayStore), 0x3c400040a0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #1723 = MOVBE16mr
19601 { 1913, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1913 = OR16mr
20238 { 2550, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x6400000a0ULL, ImplicitList1, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2550 = SBB16mr
20322 { 2634, 6, 0, 0, 640, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x29400020a0ULL, ImplicitList90, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2634 = SHLD16mrCL
20362 { 2674, 6, 0, 0, 640, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b400020a0ULL, ImplicitList90, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2674 = SHRD16mrCL
20452 { 2764, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2764 = SUB16mr
20567 { 2879, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x21400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2879 = TEST16mr
32878 { 15190, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #15190 = XOR16mr