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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17938 { 250, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #250 = XOR64_FP
18224 { 536, 2, 1, 0, 53, 0, 0x3200012002ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #536 = BSWAP64r
18542 { 854, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0010039ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #854 = DEC64r
18778 { 1090, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0010038ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #1090 = INC64r
19580 { 1892, 2, 1, 0, 1, 0, 0x3dc001003bULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #1892 = NEG64r
19595 { 1907, 2, 1, 0, 1, 0, 0x3dc001003aULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #1907 = NOT64r
20046 { 2358, 2, 1, 0, 726, 0, 0x344001003aULL, ImplicitList1, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2358 = RCL64r1
20047 { 2359, 2, 1, 0, 1015, 0, 0x34c001003aULL, ImplicitList78, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2359 = RCL64rCL
20076 { 2388, 2, 1, 0, 726, 0, 0x344001003bULL, ImplicitList1, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2388 = RCR64r1
20077 { 2389, 2, 1, 0, 1016, 0, 0x34c001003bULL, ImplicitList78, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2389 = RCR64rCL
20103 { 2415, 2, 1, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x780013039ULL, ImplicitList23, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #2415 = RDSSPQ
20147 { 2459, 2, 1, 0, 848, 0, 0x3440010038ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2459 = ROL64r1
20148 { 2460, 2, 1, 0, 282, 0, 0x34c0010038ULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2460 = ROL64rCL
20171 { 2483, 2, 1, 0, 848, 0, 0x3440010039ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2483 = ROR64r1
20172 { 2484, 2, 1, 0, 282, 0, 0x34c0010039ULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2484 = ROR64rCL
20221 { 2533, 2, 1, 0, 290, 0, 0x344001003fULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2533 = SAR64r1
20222 { 2534, 2, 1, 0, 301, 0, 0x34c001003fULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2534 = SAR64rCL
20313 { 2625, 2, 1, 0, 290, 0, 0x344001003cULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2625 = SHL64r1
20314 { 2626, 2, 1, 0, 301, 0, 0x34c001003cULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2626 = SHL64rCL
20353 { 2665, 2, 1, 0, 290, 0, 0x344001003dULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2665 = SHR64r1
20354 { 2666, 2, 1, 0, 301, 0, 0x34c001003dULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2666 = SHR64rCL
32861 { 15173, 2, 1, 0, 578, 0, 0x2400010002ULL, ImplicitList16, ImplicitList16, OperandInfo72, -1 ,nullptr }, // Inst #15173 = XCHG64ar