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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17937 { 249, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #249 = XOR32_FP
18223 { 535, 2, 1, 0, 52, 0, 0x3200002102ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #535 = BSWAP32r
18539 { 851, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0000139ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #851 = DEC32r
18540 { 852, 2, 1, 0, 1, 0, 0x1200000102ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #852 = DEC32r_alt
18775 { 1087, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0000138ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #1087 = INC32r
18776 { 1088, 2, 1, 0, 1, 0, 0x1000000102ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #1088 = INC32r_alt
19578 { 1890, 2, 1, 0, 1, 0, 0x3dc000013bULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #1890 = NEG32r
19593 { 1905, 2, 1, 0, 1, 0, 0x3dc000013aULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #1905 = NOT32r
20040 { 2352, 2, 1, 0, 726, 0, 0x344000013aULL, ImplicitList1, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2352 = RCL32r1
20041 { 2353, 2, 1, 0, 1015, 0, 0x34c000013aULL, ImplicitList78, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2353 = RCL32rCL
20070 { 2382, 2, 1, 0, 726, 0, 0x344000013bULL, ImplicitList1, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2382 = RCR32r1
20071 { 2383, 2, 1, 0, 1016, 0, 0x34c000013bULL, ImplicitList78, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2383 = RCR32rCL
20102 { 2414, 2, 1, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x780003039ULL, ImplicitList23, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #2414 = RDSSPD
20141 { 2453, 2, 1, 0, 848, 0, 0x3440000138ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2453 = ROL32r1
20142 { 2454, 2, 1, 0, 282, 0, 0x34c0000138ULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2454 = ROL32rCL
20165 { 2477, 2, 1, 0, 848, 0, 0x3440000139ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2477 = ROR32r1
20166 { 2478, 2, 1, 0, 282, 0, 0x34c0000139ULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2478 = ROR32rCL
20215 { 2527, 2, 1, 0, 290, 0, 0x344000013fULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2527 = SAR32r1
20216 { 2528, 2, 1, 0, 301, 0, 0x34c000013fULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2528 = SAR32rCL
20307 { 2619, 2, 1, 0, 290, 0, 0x344000013cULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2619 = SHL32r1
20308 { 2620, 2, 1, 0, 301, 0, 0x34c000013cULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2620 = SHL32rCL
20347 { 2659, 2, 1, 0, 290, 0, 0x344000013dULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2659 = SHR32r1
20348 { 2660, 2, 1, 0, 301, 0, 0x34c000013dULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2660 = SHR32rCL
32858 { 15170, 2, 1, 0, 578, 0, 0x2400000102ULL, ImplicitList7, ImplicitList7, OperandInfo71, -1 ,nullptr }, // Inst #15170 = XCHG32ar