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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17918 { 230, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #230 = SETB_C16r
18279 { 591, 1, 0, 0, 951, 0|(1ULL<<MCID::Call), 0x3fc00000baULL, ImplicitList17, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #591 = CALL16r
18280 { 592, 1, 0, 0, 951, 0|(1ULL<<MCID::Call), 0x20003fc00000baULL, ImplicitList17, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #592 = CALL16r_NT
18546 { 858, 1, 0, 0, 114, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc00000beULL, ImplicitList34, ImplicitList35, OperandInfo65, -1 ,nullptr }, // Inst #858 = DIV16r
18720 { 1032, 1, 0, 0, 145, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc00000bfULL, ImplicitList34, ImplicitList35, OperandInfo65, -1 ,nullptr }, // Inst #1032 = IDIV16r
18740 { 1052, 1, 0, 0, 153, 0, 0x3dc00000bdULL, ImplicitList10, ImplicitList35, OperandInfo65, -1 ,nullptr }, // Inst #1052 = IMUL16r
18842 { 1154, 1, 0, 0, 816, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x3fc00000bcULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1154 = JMP16r
18843 { 1155, 1, 0, 0, 816, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x20003fc00000bcULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1155 = JMP16r_NT
18982 { 1294, 1, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x203aULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1294 = LLDT16r
18986 { 1298, 1, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000203eULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1298 = LMSW16r
19074 { 1386, 1, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x203bULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1386 = LTRr
19529 { 1841, 1, 0, 0, 153, 0, 0x3dc00000bcULL, ImplicitList10, ImplicitList35, OperandInfo65, -1 ,nullptr }, // Inst #1841 = MUL16r
19589 { 1901, 1, 0, 0, 80, 0, 0x7c00020b7ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1901 = NOOPWr
19872 { 2184, 1, 1, 0, 605, 0|(1ULL<<MCID::MayLoad), 0x1600000082ULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2184 = POP16r
19874 { 2186, 1, 1, 0, 593, 0|(1ULL<<MCID::MayLoad), 0x23c00000b8ULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2186 = POP16rmr
19996 { 2308, 1, 0, 0, 841, 0|(1ULL<<MCID::MayStore), 0x1400000082ULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2308 = PUSH16r
19998 { 2310, 1, 0, 0, 732, 0|(1ULL<<MCID::MayStore), 0x3fc00000beULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2310 = PUSH16rmr
20096 { 2408, 1, 1, 0, 799, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c00020beULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #2408 = RDRAND16r
20099 { 2411, 1, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c00020bfULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #2411 = RDSEED16r
20391 { 2703, 1, 1, 0, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20b8ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2703 = SLDT16r
20397 { 2709, 1, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400020bcULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2709 = SMSW16r
20427 { 2739, 1, 1, 0, 891, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20b9ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2739 = STR16r
20627 { 2939, 1, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000323eULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2939 = UMONITOR16
22504 { 4816, 1, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x203cULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #4816 = VERRr
22506 { 4818, 1, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x203dULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #4818 = VERWr