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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc21252 { 3564, 2, 1, 0, 1138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40162bc004830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #3564 = VCOMPRESSPDZ256rr
21267 { 3579, 2, 1, 0, 1138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40122bc004830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #3579 = VCOMPRESSPSZ256rr
21323 { 3635, 2, 1, 0, 1108, 0, 0x40116f0002031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #3635 = VCVTDQ2PSZ256rr
21477 { 3789, 2, 1, 0, 1110, 0, 0x4015ef0002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #3789 = VCVTPD2QQZ256rr
21537 { 3849, 2, 1, 0, 1110, 0, 0x4015e70002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #3849 = VCVTPD2UQQZ256rr
21594 { 3906, 2, 1, 0, 1113, 0, 0x40116f0002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #3906 = VCVTPS2DQZ256rr
21712 { 4024, 2, 1, 0, 1113, 0, 0x4011e70002031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #4024 = VCVTPS2UDQZ256rr
21772 { 4084, 2, 1, 0, 1115, 0, 0x40179b0003031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #4084 = VCVTQQ2PDZ256rr
21963 { 4275, 2, 1, 0, 1110, 0, 0x4015eb0002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #4275 = VCVTTPD2QQZ256rr
22023 { 4335, 2, 1, 0, 1110, 0, 0x4015e30002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #4335 = VCVTTPD2UQQZ256rr
22055 { 4367, 2, 1, 0, 1113, 0, 0x40116f0003031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #4367 = VCVTTPS2DQZ256rr
22117 { 4429, 2, 1, 0, 1113, 0, 0x4011e30002031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #4429 = VCVTTPS2UDQZ256rr
22260 { 4572, 2, 1, 0, 1108, 0, 0x4011eb0003831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #4572 = VCVTUDQ2PSZ256rr
22290 { 4602, 2, 1, 0, 1115, 0, 0x4015eb0003031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #4602 = VCVTUQQ2PDZ256rr
22540 { 4852, 2, 1, 0, 1120, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x401623c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #4852 = VEXPANDPDZ256rr
22558 { 4870, 2, 1, 0, 1120, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x401223c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #4870 = VEXPANDPSZ256rr
24580 { 6892, 2, 1, 0, 432, 0, 0x40150b8004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #6892 = VGETEXPPDZ256r
24610 { 6922, 2, 1, 0, 432, 0, 0x40110b4004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #6922 = VGETEXPPSZ256r
25283 { 7595, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4014a38002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7595 = VMOVAPDZ256rr
25284 { 7596, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4014a78002830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7596 = VMOVAPDZ256rr_REV
25324 { 7636, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4010a34002031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7636 = VMOVAPSZ256rr
25325 { 7637, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4010a74002030ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7637 = VMOVAPSZ256rr_REV
25356 { 7668, 2, 1, 0, 458, 0, 0x40144b8003831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7668 = VMOVDDUPZ256rr
25389 { 7701, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011bfc002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7701 = VMOVDQA32Z256rr
25390 { 7702, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011ffc002830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7702 = VMOVDQA32Z256rr_REV
25422 { 7734, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015bfc002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7734 = VMOVDQA64Z256rr
25423 { 7735, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015ffc002830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7735 = VMOVDQA64Z256rr_REV
25463 { 7775, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015bfc003831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7775 = VMOVDQU16Z256rr
25464 { 7776, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015ffc003830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7776 = VMOVDQU16Z256rr_REV
25496 { 7808, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011bfc003031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7808 = VMOVDQU32Z256rr
25497 { 7809, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011ffc003030ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7809 = VMOVDQU32Z256rr_REV
25529 { 7841, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015bfc003031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7841 = VMOVDQU64Z256rr
25530 { 7842, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4015ffc003030ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7842 = VMOVDQU64Z256rr_REV
25562 { 7874, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011bfc003831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7874 = VMOVDQU8Z256rr
25563 { 7875, 2, 1, 0, 462, 0|(1ULL<<MCID::MoveReg), 0x4011ffc003830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7875 = VMOVDQU8Z256rr_REV
25675 { 7987, 2, 1, 0, 458, 0, 0x40105b4003031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #7987 = VMOVSHDUPZ256rr
25697 { 8009, 2, 1, 0, 458, 0, 0x40104b4003031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8009 = VMOVSLDUPZ256rr
25747 { 8059, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4014438002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8059 = VMOVUPDZ256rr
25748 { 8060, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4014478002830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8060 = VMOVUPDZ256rr_REV
25788 { 8100, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4010434002031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8100 = VMOVUPSZ256rr
25789 { 8101, 2, 1, 0, 456, 0|(1ULL<<MCID::MoveReg), 0x4010474002030ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8101 = VMOVUPSZ256rr_REV
26027 { 8339, 2, 1, 0, 440, 0, 0x401073c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8339 = VPABSBZ256rr
26055 { 8367, 2, 1, 0, 440, 0, 0x40107bc004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8367 = VPABSDZ256rr
26084 { 8396, 2, 1, 0, 440, 0, 0x40147fc004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8396 = VPABSQZ256rr
26107 { 8419, 2, 1, 0, 440, 0, 0x401077c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #8419 = VPABSWZ256rr
27141 { 9453, 2, 1, 0, 360, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40118fc004830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #9453 = VPCOMPRESSBZ256rr
27156 { 9468, 2, 1, 0, 1138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40122fc004830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #9468 = VPCOMPRESSDZ256rr
27171 { 9483, 2, 1, 0, 1138, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40162fc004830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #9483 = VPCOMPRESSQZ256rr
27186 { 9498, 2, 1, 0, 360, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40158fc004830ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #9498 = VPCOMPRESSWZ256rr
27221 { 9533, 2, 1, 0, 1263, 0, 0x401313c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #9533 = VPCONFLICTDZ256rr
27248 { 9560, 2, 1, 0, 1257, 0, 0x401713c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #9560 = VPCONFLICTQZ256rr
27961 { 10273, 2, 1, 0, 360, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40118bc004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #10273 = VPEXPANDBZ256rr
27979 { 10291, 2, 1, 0, 1120, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x401227c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #10291 = VPEXPANDDZ256rr
27997 { 10309, 2, 1, 0, 1120, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x401627c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #10309 = VPEXPANDQZ256rr
28015 { 10327, 2, 1, 0, 360, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40158bc004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #10327 = VPEXPANDWZ256rr
28149 { 10461, 2, 1, 0, 436, 0, 0x401113c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #10461 = VPLZCNTDZ256rr
28176 { 10488, 2, 1, 0, 436, 0, 0x401513c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #10488 = VPLZCNTQZ256rr
29530 { 11842, 2, 1, 0, 440, 0, 0x401153c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #11842 = VPOPCNTBZ256rr
29554 { 11866, 2, 1, 0, 440, 0, 0x401157c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #11866 = VPOPCNTDZ256rr
29581 { 11893, 2, 1, 0, 440, 0, 0x401557c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #11893 = VPOPCNTQZ256rr
29602 { 11914, 2, 1, 0, 440, 0, 0x401553c004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #11914 = VPOPCNTWZ256rr
31789 { 14101, 2, 1, 0, 548, 0, 0x4015338004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #14101 = VRCP14PDZ256r
31816 { 14128, 2, 1, 0, 548, 0, 0x4011334004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #14128 = VRCP14PSZ256r
32081 { 14393, 2, 1, 0, 555, 0, 0x40153b8004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #14393 = VRSQRT14PDZ256r
32108 { 14420, 2, 1, 0, 555, 0, 0x40113b4004831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #14420 = VRSQRT14PSZ256r
32431 { 14743, 2, 1, 0, 562, 0, 0x4015478002831ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #14743 = VSQRTPDZ256r
32465 { 14777, 2, 1, 0, 568, 0, 0x4011474002031ULL, nullptr, nullptr, OperandInfo481, -1 ,nullptr }, // Inst #14777 = VSQRTPSZ256r