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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17870 { 182, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #182 = ADD64rr_DB
17972 { 284, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x440010030ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #284 = ADC64rr
17973 { 285, 3, 1, 0, 16, 0, 0x4c0010031ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #285 = ADC64rr_REV
17986 { 298, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80014831ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #298 = ADCX64rr
18012 { 324, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x40010030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #324 = ADD64rr
18013 { 325, 3, 1, 0, 1, 0, 0xc0010031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #325 = ADD64rr_REV
18067 { 379, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80015031ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #379 = ADOX64rr
18105 { 417, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x840010030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #417 = AND64rr
18106 { 418, 3, 1, 0, 1, 0, 0x8c0010031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #418 = AND64rr_REV
18248 { 560, 3, 1, 0, 59, 0, 0x2ec0012030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #560 = BTC64rr
18260 { 572, 3, 1, 0, 59, 0, 0x2cc0012030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #572 = BTR64rr
18272 { 584, 3, 1, 0, 59, 0, 0x2ac0012030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #584 = BTS64rr
18463 { 775, 3, 1, 0, 1008, 0, 0x3c40015831ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #775 = CRC32r64r64
18760 { 1072, 3, 1, 0, 168, 0|(1ULL<<MCID::Commutable), 0x2bc0012031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #1072 = IMUL64rr
19624 { 1936, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x240010030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #1936 = OR64rr
19625 { 1937, 3, 1, 0, 1, 0, 0x2c0010031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #1937 = OR64rr_REV
20260 { 2572, 3, 1, 0, 16, 0, 0x640010030ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2572 = SBB64rr
20261 { 2573, 3, 1, 0, 16, 0, 0x6c0010031ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2573 = SBB64rr_REV
20332 { 2644, 3, 1, 0, 647, 0, 0x2940012030ULL, ImplicitList90, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2644 = SHLD64rrCL
20372 { 2684, 3, 1, 0, 647, 0, 0x2b40012030ULL, ImplicitList90, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2684 = SHRD64rrCL
20474 { 2786, 3, 1, 0, 784, 0|(1ULL<<MCID::Compare), 0xa40010030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2786 = SUB64rr
20475 { 2787, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare), 0xac0010031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2787 = SUB64rr_REV
32900 { 15212, 3, 1, 0, 784, 0|(1ULL<<MCID::Commutable), 0xc40010030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #15212 = XOR64rr
32901 { 15213, 3, 1, 0, 1, 0, 0xcc0010031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #15213 = XOR64rr_REV