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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17867 { 179, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #179 = ADD32rr_DB
17963 { 275, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x440000130ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #275 = ADC32rr
17964 { 276, 3, 1, 0, 16, 0, 0x4c0000131ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #276 = ADC32rr_REV
17984 { 296, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80004831ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #296 = ADCX32rr
18003 { 315, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x40000130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #315 = ADD32rr
18004 { 316, 3, 1, 0, 1, 0, 0xc0000131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #316 = ADD32rr_REV
18065 { 377, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80005031ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #377 = ADOX32rr
18096 { 408, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x840000130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #408 = AND32rr
18097 { 409, 3, 1, 0, 1, 0, 0x8c0000131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #409 = AND32rr_REV
18244 { 556, 3, 1, 0, 59, 0, 0x2ec0002130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #556 = BTC32rr
18256 { 568, 3, 1, 0, 59, 0, 0x2cc0002130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #568 = BTR32rr
18268 { 580, 3, 1, 0, 59, 0, 0x2ac0002130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #580 = BTS32rr
18459 { 771, 3, 1, 0, 1007, 0, 0x3c40005931ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #771 = CRC32r32r32
18752 { 1064, 3, 1, 0, 162, 0|(1ULL<<MCID::Commutable), 0x2bc0002131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #1064 = IMUL32rr
19615 { 1927, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x240000130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #1927 = OR32rr
19616 { 1928, 3, 1, 0, 1, 0, 0x2c0000131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #1928 = OR32rr_REV
20251 { 2563, 3, 1, 0, 16, 0, 0x640000130ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2563 = SBB32rr
20252 { 2564, 3, 1, 0, 16, 0, 0x6c0000131ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2564 = SBB32rr_REV
20328 { 2640, 3, 1, 0, 956, 0, 0x2940002130ULL, ImplicitList90, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2640 = SHLD32rrCL
20368 { 2680, 3, 1, 0, 956, 0, 0x2b40002130ULL, ImplicitList90, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2680 = SHRD32rrCL
20465 { 2777, 3, 1, 0, 784, 0|(1ULL<<MCID::Compare), 0xa40000130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2777 = SUB32rr
20466 { 2778, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare), 0xac0000131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2778 = SUB32rr_REV
32891 { 15203, 3, 1, 0, 784, 0|(1ULL<<MCID::Commutable), 0xc40000130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #15203 = XOR32rr
32892 { 15204, 3, 1, 0, 1, 0, 0xcc0000131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #15204 = XOR32rr_REV