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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17865 { 177, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #177 = ADD32ri8_DB
17866 { 178, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #178 = ADD32ri_DB
17922 { 234, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #234 = SHLDROT32ri
17924 { 236, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #236 = SHRDROT32ri
17960 { 272, 3, 1, 0, 16, 0, 0x20400c013aULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #272 = ADC32ri
17961 { 273, 3, 1, 0, 925, 0, 0x20c002013aULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #273 = ADC32ri8
18000 { 312, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400c0138ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #312 = ADD32ri
18001 { 313, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c0020138ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #313 = ADD32ri8
18093 { 405, 3, 1, 0, 1, 0, 0x20400c013cULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #405 = AND32ri
18094 { 406, 3, 1, 0, 1, 0, 0x20c002013cULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #406 = AND32ri8
18243 { 555, 3, 1, 0, 59, 0, 0x2e8002213fULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #555 = BTC32ri8
18255 { 567, 3, 1, 0, 59, 0, 0x2e8002213eULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #567 = BTR32ri8
18267 { 579, 3, 1, 0, 59, 0, 0x2e8002213dULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #579 = BTS32ri8
19612 { 1924, 3, 1, 0, 1, 0, 0x20400c0139ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #1924 = OR32ri
19613 { 1925, 3, 1, 0, 1, 0, 0x20c0020139ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #1925 = OR32ri8
20042 { 2354, 3, 1, 0, 1019, 0, 0x304002013aULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2354 = RCL32ri
20072 { 2384, 3, 1, 0, 1017, 0, 0x304002013bULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2384 = RCR32ri
20143 { 2455, 3, 1, 0, 281, 0, 0x3040020138ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2455 = ROL32ri
20167 { 2479, 3, 1, 0, 281, 0, 0x3040020139ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2479 = ROR32ri
20217 { 2529, 3, 1, 0, 290, 0, 0x304002013fULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2529 = SAR32ri
20248 { 2560, 3, 1, 0, 16, 0, 0x20400c013bULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2560 = SBB32ri
20249 { 2561, 3, 1, 0, 925, 0, 0x20c002013bULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2561 = SBB32ri8
20309 { 2621, 3, 1, 0, 290, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x304002013cULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2621 = SHL32ri
20349 { 2661, 3, 1, 0, 290, 0, 0x304002013dULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2661 = SHR32ri
20462 { 2774, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400c013dULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2774 = SUB32ri
20463 { 2775, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c002013dULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2775 = SUB32ri8
32888 { 15200, 3, 1, 0, 1, 0, 0x20400c013eULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #15200 = XOR32ri
32889 { 15201, 3, 1, 0, 1, 0, 0x20c002013eULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #15201 = XOR32ri8